Flutter Engine
The Flutter Engine
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#include "platform/assert.h"
#include "platform/globals.h"
#include "platform/utils.h"
#include "vm/constants_base.h"
Go to the source code of this file.
Namespaces | |
namespace | dart |
Macros | |
#define | LR LR_DO_NOT_USE_DIRECTLY |
#define | DART_ASSEMBLER_HAS_NULL_REG 1 |
#define | R(reg) (static_cast<RegList>(1) << (reg)) |
#define | APPLY_OP_LIST(_V) |
#define | IS_OP(op) |
#define | LINK_REGISTER (LinkRegister()) |
Enumerations | |
enum | dart::Register { dart::R0 = 0 , dart::R1 = 1 , dart::R2 = 2 , dart::R3 = 3 , dart::R4 = 4 , dart::R5 = 5 , dart::R6 = 6 , dart::R7 = 7 , dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 , dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::FP = R11 , dart::NOTFP = R7 , dart::IP = R12 , dart::SP = R13 , dart::LR = R14 , dart::PC = R15 , dart::R0 = 0 , dart::R1 = 1 , dart::R2 = 2 , dart::R3 = 3 , dart::R4 = 4 , dart::R5 = 5 , dart::R6 = 6 , dart::R7 = 7 , dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 , dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 , dart::R16 = 16 , dart::R17 = 17 , dart::R18 = 18 , dart::R19 = 19 , dart::R20 = 20 , dart::R21 = 21 , dart::R22 = 22 , dart::R23 = 23 , dart::R24 = 24 , dart::R25 = 25 , dart::R26 = 26 , dart::R27 = 27 , dart::R28 = 28 , dart::R29 = 29 , dart::R30 = 30 , dart::R31 = 31 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::kNoRegister2 = -2 , dart::CSP = 32 , dart::ZR = 33 , dart::IP0 = R16 , dart::IP1 = R17 , dart::SP = R13 , dart::FP = R11 , dart::LR = R14 , dart::EAX = 0 , dart::ECX = 1 , dart::EDX = 2 , dart::EBX = 3 , dart::ESP = 4 , dart::EBP = 5 , dart::ESI = 6 , dart::EDI = 7 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::ZR = 33 , dart::RA = 1 , dart::SP = R13 , dart::GP = 3 , dart::TP = 4 , dart::T0 = 5 , dart::T1 = 6 , dart::T2 = 7 , dart::FP = R11 , dart::S1 = 1 , dart::A0 = 10 , dart::A1 = 11 , dart::A2 = 12 , dart::A3 = 13 , dart::A4 = 14 , dart::A5 = 15 , dart::A6 = 16 , dart::A7 = 17 , dart::S2 = 2 , dart::S3 = 3 , dart::S4 = 4 , dart::S5 = 5 , dart::S6 = 6 , dart::S7 = 7 , dart::S8 = 8 , dart::S9 = 9 , dart::S10 = 10 , dart::S11 = 11 , dart::T3 = 28 , dart::T4 = 29 , dart::T5 = 30 , dart::T6 = 31 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::RA2 = T0 , dart::S0 = 0 , dart::RAX = 0 , dart::RCX = 1 , dart::RDX = 2 , dart::RBX = 3 , dart::RSP = 4 , dart::RBP = 5 , dart::RSI = 6 , dart::RDI = 7 , dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 , dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 } |
enum | dart::VRegister { dart::V0 = 0 , dart::V1 = 1 , dart::V2 = 2 , dart::V3 = 3 , dart::V4 = 4 , dart::V5 = 5 , dart::V6 = 6 , dart::V7 = 7 , dart::V8 = 8 , dart::V9 = 9 , dart::V10 = 10 , dart::V11 = 11 , dart::V12 = 12 , dart::V13 = 13 , dart::V14 = 14 , dart::V15 = 15 , dart::V16 = 16 , dart::V17 = 17 , dart::V18 = 18 , dart::V19 = 19 , dart::V20 = 20 , dart::V21 = 21 , dart::V22 = 22 , dart::V23 = 23 , dart::V24 = 24 , dart::V25 = 25 , dart::V26 = 26 , dart::V27 = 27 , dart::V28 = 28 , dart::V29 = 29 , dart::V30 = 30 , dart::V31 = 31 , dart::kNumberOfVRegisters = 32 , dart::kNoVRegister = -1 } |
enum | dart::Condition { dart::kNoCondition = -1 , dart::EQ = 0 , dart::NE = 1 , dart::CS = 2 , dart::CC = 3 , dart::MI = 4 , dart::PL = 5 , dart::VS = 6 , dart::VC = 7 , dart::HI = 8 , dart::LS = 9 , dart::GE = 10 , dart::LT = 11 , dart::GT = 12 , dart::LE = 13 , dart::AL = 14 , dart::kSpecialCondition = 15 , dart::kNumberOfConditions = 16 , dart::EQUAL = EQ , dart::ZERO = EQUAL , dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL , dart::LESS = LT , dart::LESS_EQUAL = LE , dart::GREATER_EQUAL = GE , dart::GREATER = GT , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC , dart::kInvalidCondition = 16 , dart::kNoCondition = -1 , dart::EQ = 0 , dart::NE = 1 , dart::CS = 2 , dart::CC = 3 , dart::MI = 4 , dart::PL = 5 , dart::VS = 6 , dart::VC = 7 , dart::HI = 8 , dart::LS = 9 , dart::GE = 10 , dart::LT = 11 , dart::GT = 12 , dart::LE = 13 , dart::AL = 14 , dart::NV = 15 , dart::kNumberOfConditions = 16 , dart::EQUAL = EQ , dart::ZERO = EQUAL , dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL , dart::LESS = LT , dart::LESS_EQUAL = LE , dart::GREATER_EQUAL = GE , dart::GREATER = GT , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC , dart::kInvalidCondition = 16 , dart::kNoCondition = -1 , dart::EQ = 0 , dart::NE = 1 , dart::CS = 2 , dart::CC = 3 , dart::MI = 4 , dart::PL = 5 , dart::VS = 6 , dart::VC = 7 , dart::HI = 8 , dart::LS = 9 , dart::GE = 10 , dart::LT = 11 , dart::GT = 12 , dart::LE = 13 , dart::AL = 14 , dart::NV = 15 , dart::kNumberOfConditions = 16 , dart::EQUAL = EQ , dart::ZERO = EQUAL , dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL , dart::LESS = LT , dart::LESS_EQUAL = LE , dart::GREATER_EQUAL = GE , dart::GREATER = GT , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC , dart::kInvalidCondition = 16 , dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC , dart::BELOW = 2 , dart::ABOVE_EQUAL = 3 , dart::EQUAL = EQ , dart::NOT_EQUAL = NE , dart::BELOW_EQUAL = 6 , dart::ABOVE = 7 , dart::SIGN = 8 , dart::NOT_SIGN = 9 , dart::PARITY_EVEN = 10 , dart::PARITY_ODD = 11 , dart::LESS = LT , dart::GREATER_EQUAL = GE , dart::LESS_EQUAL = LE , dart::GREATER = GT , dart::ZERO = EQUAL , dart::NOT_ZERO = NOT_EQUAL , dart::NEGATIVE = SIGN , dart::POSITIVE = NOT_SIGN , dart::CARRY = BELOW , dart::NOT_CARRY = ABOVE_EQUAL , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::kInvalidCondition = 16 } |
enum | dart::Bits { dart::B0 = (1 << 0) , dart::B1 = (1 << 1) , dart::B2 = (1 << 2) , dart::B3 = (1 << 3) , dart::B4 = (1 << 4) , dart::B5 = (1 << 5) , dart::B6 = (1 << 6) , dart::B7 = (1 << 7) , dart::B8 = (1 << 8) , dart::B9 = (1 << 9) , dart::B10 = (1 << 10) , dart::B11 = (1 << 11) , dart::B12 = (1 << 12) , dart::B13 = (1 << 13) , dart::B14 = (1 << 14) , dart::B15 = (1 << 15) , dart::B16 = (1 << 16) , dart::B17 = (1 << 17) , dart::B18 = (1 << 18) , dart::B19 = (1 << 19) , dart::B20 = (1 << 20) , dart::B21 = (1 << 21) , dart::B22 = (1 << 22) , dart::B23 = (1 << 23) , dart::B24 = (1 << 24) , dart::B25 = (1 << 25) , dart::B26 = (1 << 26) , dart::B27 = (1 << 27) , dart::B28 = (1 << 28) , dart::B29 = (1 << 29) , dart::B30 = (1 << 30) , dart::B31 = (1 << 31) } |
enum | dart::MainOp { dart::DPImmediateMask = 0x1c000000 , dart::DPImmediateFixed = B28 , dart::CompareBranchMask = 0x1c000000 , dart::CompareBranchFixed = B28 | B26 , dart::LoadStoreMask = B27 | B25 , dart::LoadStoreFixed = B27 , dart::DPRegisterMask = 0x0e000000 , dart::DPRegisterFixed = B27 | B25 , dart::DPSimd1Mask = 0x1e000000 , dart::DPSimd1Fixed = B27 | B26 | B25 , dart::DPSimd2Mask = 0x1e000000 , dart::DPSimd2Fixed = B28 | DPSimd1Fixed , dart::FPMask = 0x5e000000 , dart::FPFixed = B28 | B27 | B26 | B25 } |
enum | dart::CompareAndBranchOp { dart::CompareAndBranchMask = 0x7e000000 , dart::CompareAndBranchFixed = CompareBranchFixed | B29 , dart::CBZ = CompareAndBranchFixed , dart::CBNZ = CompareAndBranchFixed | B24 } |
enum | dart::ConditionalBranchOp { dart::ConditionalBranchMask = 0xfe000000 , dart::ConditionalBranchFixed = CompareBranchFixed | B30 , dart::BCOND = ConditionalBranchFixed } |
enum | dart::ExceptionGenOp { dart::ExceptionGenMask = 0xff000000 , dart::ExceptionGenFixed = CompareBranchFixed | B31 | B30 , dart::SVC = ExceptionGenFixed | B0 , dart::BRK = ExceptionGenFixed | B21 , dart::HLT = ExceptionGenFixed | B22 } |
enum | dart::SystemOp { dart::SystemMask = 0xffc00000 , dart::SystemFixed = CompareBranchFixed | B31 | B30 | B24 , dart::HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0 , dart::CLREX } |
enum | dart::TestAndBranchOp { dart::TestAndBranchMask = 0x7e000000 , dart::TestAndBranchFixed = CompareBranchFixed | B29 | B25 , dart::TBZ = TestAndBranchFixed , dart::TBNZ = TestAndBranchFixed | B24 } |
enum | dart::UnconditionalBranchOp { dart::UnconditionalBranchMask = 0x7c000000 , dart::UnconditionalBranchFixed = CompareBranchFixed , dart::B = UnconditionalBranchFixed , dart::BL = UnconditionalBranchFixed | B31 } |
enum | dart::UnconditionalBranchRegOp { dart::UnconditionalBranchRegMask = 0xfe000000 , dart::UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25 , dart::BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16 , dart::BLR = BR | B21 , dart::RET = BR | B22 } |
enum | dart::LoadRegLiteralOp { dart::LoadRegLiteralMask = 0x3b000000 , dart::LoadRegLiteralFixed = LoadStoreFixed | B28 , dart::LDRpc = LoadRegLiteralFixed } |
enum | dart::LoadStoreExclusiveOp { dart::LoadStoreExclusiveMask = 0x3f000000 , dart::LoadStoreExclusiveFixed = B27 , dart::LDXR = LoadStoreExclusiveFixed | B22 , dart::STXR = LoadStoreExclusiveFixed , dart::LDAR = LoadStoreExclusiveFixed | B23 | B22 | B15 , dart::STLR = LoadStoreExclusiveFixed | B23 | B15 } |
enum | dart::AtomicMemoryOp { dart::AtomicMemoryMask = 0x3f200c00 , dart::AtomicMemoryFixed = B29 | B28 | B27 | B21 , dart::LDCLR = AtomicMemoryFixed | B12 , dart::LDSET = AtomicMemoryFixed | B13 | B12 } |
enum | dart::LoadStoreRegOp { dart::LoadStoreRegMask = 0x3a000000 , dart::LoadStoreRegFixed = LoadStoreFixed | B29 | B28 , dart::STR = LoadStoreRegFixed , dart::LDR = LoadStoreRegFixed | B22 , dart::LDRS = LoadStoreRegFixed | B23 , dart::FSTR = STR | B26 , dart::FLDR = LDR | B26 , dart::FSTRQ = STR | B26 | B23 , dart::FLDRQ = LDR | B26 | B23 } |
enum | dart::LoadStoreRegPairOp { dart::LoadStoreRegPairMask = 0x3a000000 , dart::LoadStoreRegPairFixed = LoadStoreFixed | B29 , dart::STP = LoadStoreRegPairFixed , dart::LDP = LoadStoreRegPairFixed | B22 , dart::FSTP = STP | B26 , dart::FLDP = LDP | B26 } |
enum | dart::AddSubImmOp { dart::AddSubImmMask = 0x1f000000 , dart::AddSubImmFixed = DPImmediateFixed | B24 , dart::ADDI = AddSubImmFixed , dart::SUBI = AddSubImmFixed | B30 } |
enum | dart::BitfieldOp { dart::BitfieldMask = 0x1f800000 , dart::BitfieldFixed = 0x13000000 , dart::SBFM = BitfieldFixed , dart::BFM = BitfieldFixed | B29 , dart::UBFM = BitfieldFixed | B30 , dart::Bitfield64 = B31 | B22 } |
enum | dart::LogicalImmOp { dart::LogicalImmMask = 0x1f800000 , dart::LogicalImmFixed = DPImmediateFixed | B25 , dart::ANDI = LogicalImmFixed , dart::ORRI = LogicalImmFixed | B29 , dart::EORI = LogicalImmFixed | B30 , dart::ANDIS = LogicalImmFixed | B30 | B29 } |
enum | dart::MoveWideOp { dart::MoveWideMask = 0x1f800000 , dart::MoveWideFixed = DPImmediateFixed | B25 | B23 , dart::MOVN = MoveWideFixed , dart::MOVZ = MoveWideFixed | B30 , dart::MOVK = MoveWideFixed | B30 | B29 } |
enum | dart::PCRelOp { dart::PCRelMask = 0x1f000000 , dart::PCRelFixed = DPImmediateFixed , dart::ADR = PCRelFixed , dart::ADRP = PCRelFixed | B31 } |
enum | dart::AddSubShiftExtOp { dart::AddSubShiftExtMask = 0x1f000000 , dart::AddSubShiftExtFixed = DPRegisterFixed | B24 , dart::ADD = 4 , dart::SUB = 2 } |
enum | dart::AddSubWithCarryOp { dart::AddSubWithCarryMask = 0x1fe00000 , dart::AddSubWithCarryFixed = DPRegisterFixed | B28 , dart::ADC = 5 , dart::SBC = 6 } |
enum | dart::ConditionalSelectOp { dart::ConditionalSelectMask = 0x1fe00000 , dart::ConditionalSelectFixed = DPRegisterFixed | B28 | B23 , dart::CSEL = ConditionalSelectFixed , dart::CSINC = ConditionalSelectFixed | B10 , dart::CSINV = ConditionalSelectFixed | B30 , dart::CSNEG = ConditionalSelectFixed | B10 | B30 } |
enum | dart::MiscDP1SourceOp { dart::MiscDP1SourceMask = 0x5fe00000 , dart::MiscDP1SourceFixed = DPRegisterFixed | B30 | B28 | B23 | B22 , dart::CLZ = MiscDP1SourceFixed | B12 , dart::RBIT = MiscDP1SourceFixed } |
enum | dart::MiscDP2SourceOp { dart::MiscDP2SourceMask = 0x5fe00000 , dart::MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22 , dart::UDIV = MiscDP2SourceFixed | B11 , dart::SDIV = MiscDP2SourceFixed | B11 | B10 , dart::LSLV = MiscDP2SourceFixed | B13 , dart::LSRV = MiscDP2SourceFixed | B13 | B10 , dart::ASRV = MiscDP2SourceFixed | B13 | B11 } |
enum | dart::MiscDP3SourceOp { dart::MiscDP3SourceMask = 0x1f000000 , dart::MiscDP3SourceFixed = DPRegisterFixed | B28 | B24 , dart::MADDW = MiscDP3SourceFixed , dart::MADD = MiscDP3SourceFixed | B31 , dart::MSUBW = MiscDP3SourceFixed | B15 , dart::MSUB = MiscDP3SourceFixed | B31 | B15 , dart::SMULH = MiscDP3SourceFixed | B31 | B22 , dart::UMULH = MiscDP3SourceFixed | B31 | B23 | B22 , dart::SMADDL = MiscDP3SourceFixed | B31 | B21 , dart::UMADDL = MiscDP3SourceFixed | B31 | B23 | B21 , dart::SMSUBL = MiscDP3SourceFixed | B31 | B21 | B15 , dart::UMSUBL = MiscDP3SourceFixed | B31 | B23 | B21 | B15 } |
enum | dart::LogicalShiftOp { dart::LogicalShiftMask = 0x1f000000 , dart::LogicalShiftFixed = DPRegisterFixed , dart::AND = 0 , dart::BIC = 14 , dart::ORR = 12 , dart::ORN = LogicalShiftFixed | B29 | B21 , dart::EOR = 1 , dart::EON = LogicalShiftFixed | B30 | B21 , dart::ANDS = LogicalShiftFixed | B30 | B29 , dart::BICS = LogicalShiftFixed | B30 | B29 | B21 } |
enum | dart::SIMDCopyOp { dart::SIMDCopyMask = 0x9fe08400 , dart::SIMDCopyFixed = DPSimd1Fixed | B10 , dart::VDUPI = SIMDCopyFixed | B30 | B11 , dart::VINSI = SIMDCopyFixed | B30 | B12 | B11 , dart::VMOVW = SIMDCopyFixed | B13 | B12 | B11 , dart::VMOVX = SIMDCopyFixed | B30 | B13 | B12 | B11 , dart::VDUP = SIMDCopyFixed | B30 , dart::VINS = SIMDCopyFixed | B30 | B29 } |
enum | dart::SIMDThreeSameOp { dart::SIMDThreeSameMask = 0x9f200400 , dart::SIMDThreeSameFixed = DPSimd1Fixed | B21 | B10 , dart::VAND = SIMDThreeSameFixed | B30 | B12 | B11 , dart::VORR = SIMDThreeSameFixed | B30 | B23 | B12 | B11 , dart::VEOR = SIMDThreeSameFixed | B30 | B29 | B12 | B11 , dart::VADDW = SIMDThreeSameFixed | B30 | B23 | B15 , dart::VADDX = SIMDThreeSameFixed | B30 | B23 | B22 | B15 , dart::VSUBW = SIMDThreeSameFixed | B30 | B29 | B23 | B15 , dart::VSUBX = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 , dart::VADDS = SIMDThreeSameFixed | B30 | B15 | B14 | B12 , dart::VADDD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B12 , dart::VSUBS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B12 , dart::VSUBD = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B12 , dart::VMULS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B12 | B11 , dart::VMULD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B12 | B11 , dart::VDIVS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 | B12 | B11 , dart::VDIVD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 | B12 | B11 , dart::VCEQS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 , dart::VCEQD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 , dart::VCGES = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 , dart::VCGED = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 , dart::VCGTS = SIMDThreeSameFixed | B30 | B29 | B23 | B15 | B14 | B13 , dart::VCGTD = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 , dart::VMAXS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 , dart::VMAXD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 | B12 , dart::VMINS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 , dart::VMIND = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VRECPSS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 | B11 , dart::VRSQRTSS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 | B11 } |
enum | dart::SIMDTwoRegOp { dart::SIMDTwoRegMask = 0x9f3e0c00 , dart::SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11 , dart::VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12 , dart::VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12 , dart::VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12 , dart::VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VSQRTS = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B13 | B12 , dart::VSQRTD , dart::VRECPES = SIMDTwoRegFixed | B30 | B23 | B16 | B15 | B14 | B12 , dart::VRSQRTES = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B12 } |
enum | dart::FPCompareOp { dart::FPCompareMask = 0xffa0fc07 , dart::FPCompareFixed = FPFixed | B21 | B13 , dart::FCMPD = FPCompareFixed | B22 , dart::FCMPZD = FPCompareFixed | B22 | B3 } |
enum | dart::FPOneSourceOp { dart::FPOneSourceMask = 0x5f207c00 , dart::FPOneSourceFixed = FPFixed | B21 | B14 , dart::FMOVDD = FPOneSourceFixed | B22 , dart::FABSD = FPOneSourceFixed | B22 | B15 , dart::FNEGD = FPOneSourceFixed | B22 | B16 , dart::FSQRTD = FPOneSourceFixed | B22 | B16 | B15 , dart::FCVTDS = FPOneSourceFixed | B15 | B17 , dart::FCVTSD = FPOneSourceFixed | B22 | B17 } |
enum | dart::FPTwoSourceOp { dart::FPTwoSourceMask = 0xff200c00 , dart::FPTwoSourceFixed = FPFixed | B21 | B11 , dart::FMULD = FPTwoSourceFixed | B22 , dart::FDIVD = FPTwoSourceFixed | B22 | B12 , dart::FADDD = FPTwoSourceFixed | B22 | B13 , dart::FSUBD = FPTwoSourceFixed | B22 | B13 | B12 } |
enum | dart::FPImmOp { dart::FPImmMask = 0x5f201c00 , dart::FPImmFixed = FPFixed | B21 | B12 , dart::FMOVSI = FPImmFixed , dart::FMOVDI = FPImmFixed | B22 } |
enum | dart::FPIntCvtOp { dart::FPIntCvtMask = 0x5f00fc00 , dart::FPIntCvtFixed = FPFixed | B21 , dart::FMOVRS = FPIntCvtFixed | B18 | B17 , dart::FMOVSR = FPIntCvtFixed | B18 | B17 | B16 , dart::FMOVRD = FPIntCvtFixed | B22 | B18 | B17 , dart::FMOVDR = FPIntCvtFixed | B22 | B18 | B17 | B16 , dart::FCVTZS_D = FPIntCvtFixed | B22 | B20 | B19 , dart::FCVTMS_D = FPIntCvtFixed | B22 | B20 , dart::FCVTPS_D = FPIntCvtFixed | B22 | B19 , dart::SCVTFD = FPIntCvtFixed | B22 | B17 } |
enum | dart::Shift { dart::kNoShift = -1 , dart::LSL = 0 , dart::LSR = 1 , dart::ASR = 2 , dart::ROR = 3 , dart::kMaxShift = 4 , dart::kNoShift = -1 , dart::LSL = 0 , dart::LSR = 1 , dart::ASR = 2 , dart::ROR = 3 , dart::kMaxShift = 4 } |
enum | dart::Extend { dart::kNoExtend = -1 , dart::UXTB = 0 , dart::UXTH = 1 , dart::UXTW = 2 , dart::UXTX = 3 , dart::SXTB = 4 , dart::SXTH = 5 , dart::SXTW = 6 , dart::SXTX = 7 , dart::kMaxExtend = 8 } |
enum | dart::R31Type { dart::R31IsSP , dart::R31IsZR } |
enum | dart::InstructionFields { dart::kConditionShift = 28 , dart::kConditionBits = 4 , dart::kTypeShift = 25 , dart::kTypeBits = 3 , dart::kLinkShift = 24 , dart::kLinkBits = 1 , dart::kUShift = 23 , dart::kUBits = 1 , dart::kOpcodeShift = 21 , dart::kOpcodeBits = 4 , dart::kSShift = 20 , dart::kSBits = 1 , dart::kRnShift = 16 , dart::kRnBits = 4 , dart::kRdShift = 12 , dart::kRdBits = 4 , dart::kRsShift = 8 , dart::kRsBits = 4 , dart::kRmShift = 0 , dart::kRmBits = 4 , dart::kRotateShift = 8 , dart::kRotateBits = 4 , dart::kImmed8Shift = 0 , dart::kImmed8Bits = 8 , dart::kShiftImmShift = 7 , dart::kShiftRegisterShift = 8 , dart::kShiftImmBits = 5 , dart::kShiftShift = 5 , dart::kShiftBits = 2 , dart::kOffset12Shift = 0 , dart::kOffset12Bits = 12 , dart::kOffset12Mask = 0x00000fff , dart::kMulRdShift = 16 , dart::kMulRdBits = 4 , dart::kMulRnShift = 12 , dart::kMulRnBits = 4 , dart::kLdrExRnShift = 16 , dart::kLdrExRtShift = 12 , dart::kStrExRnShift = 16 , dart::kStrExRdShift = 12 , dart::kStrExRtShift = 0 , dart::kMediaOp1Shift = 20 , dart::kMediaOp1Bits = 5 , dart::kMediaOp2Shift = 5 , dart::kMediaOp2Bits = 3 , dart::kDivRdShift = 16 , dart::kDivRdBits = 4 , dart::kDivRmShift = 8 , dart::kDivRmBits = 4 , dart::kDivRnShift = 0 , dart::kDivRnBits = 4 , dart::kBitFieldExtractWidthShift = 16 , dart::kBitFieldExtractWidthBits = 5 , dart::kBitFieldExtractLSBShift = 7 , dart::kBitFieldExtractLSBBits = 5 , dart::kBitFieldExtractRnShift = 0 , dart::kBitFieldExtractRnBits = 4 , dart::kCRmShift = 0 , dart::kCRmBits = 4 , dart::kOpc2Shift = 5 , dart::kOpc2Bits = 3 , dart::kCoprocShift = 8 , dart::kCoprocBits = 4 , dart::kCRnShift = 16 , dart::kCRnBits = 4 , dart::kOpc1Shift = 21 , dart::kOpc1Bits = 3 , dart::kBranchOffsetMask = 0x00ffffff , dart::kSShift = 20 , dart::kSBits = 1 , dart::kSFShift = 31 , dart::kSFBits = 1 , dart::kSzShift = 30 , dart::kSzBits = 2 , dart::kRdShift = 12 , dart::kRdBits = 4 , dart::kRnShift = 16 , dart::kRnBits = 4 , dart::kRaShift = 10 , dart::kRaBits = 5 , dart::kRmShift = 0 , dart::kRmBits = 4 , dart::kRtShift = 0 , dart::kRtBits = 5 , dart::kRt2Shift = 10 , dart::kRt2Bits = 5 , dart::kRsShift = 8 , dart::kRsBits = 4 , dart::kVdShift = 0 , dart::kVdBits = 5 , dart::kVnShift = 5 , dart::kVnBits = 5 , dart::kVmShift = 16 , dart::kVmBits = 5 , dart::kVtShift = 0 , dart::kVtBits = 5 , dart::kVt2Shift = 10 , dart::kVt2Bits = 5 , dart::kImm3Shift = 10 , dart::kImm3Bits = 3 , dart::kImm4Shift = 11 , dart::kImm4Bits = 4 , dart::kImm5Shift = 16 , dart::kImm5Bits = 5 , dart::kImm6Shift = 10 , dart::kImm6Bits = 6 , dart::kImm7Shift = 15 , dart::kImm7Bits = 7 , dart::kImm7Mask = 0x7f << kImm7Shift , dart::kImm8Shift = 13 , dart::kImm8Bits = 8 , dart::kImm9Shift = 12 , dart::kImm9Bits = 9 , dart::kImm12Shift = 10 , dart::kImm12Bits = 12 , dart::kImm12Mask = 0xfff << kImm12Shift , dart::kImm12ShiftShift = 22 , dart::kImm12ShiftBits = 2 , dart::kImm14Shift = 5 , dart::kImm14Bits = 14 , dart::kImm14Mask = 0x3fff << kImm14Shift , dart::kImm16Shift = 5 , dart::kImm16Bits = 16 , dart::kImm16Mask = 0xffff << kImm16Shift , dart::kImm19Shift = 5 , dart::kImm19Bits = 19 , dart::kImm19Mask = 0x7ffff << kImm19Shift , dart::kImm26Shift = 0 , dart::kImm26Bits = 26 , dart::kImm26Mask = 0x03ffffff << kImm26Shift , dart::kCondShift = 0 , dart::kCondBits = 4 , dart::kCondMask = 0xf << kCondShift , dart::kSelCondShift = 12 , dart::kSelCondBits = 4 , dart::kNShift = 22 , dart::kNBits = 1 , dart::kImmRShift = 16 , dart::kImmRBits = 6 , dart::kImmSShift = 10 , dart::kImmSBits = 6 , dart::kHWShift = 21 , dart::kHWBits = 2 , dart::kAddShiftExtendShift = 21 , dart::kAddShiftExtendBits = 1 , dart::kShiftTypeShift = 22 , dart::kShiftTypeBits = 2 , dart::kExtendTypeShift = 13 , dart::kExtendTypeBits = 3 , dart::kHintCRmShift = 8 , dart::kHintCRmBits = 4 , dart::kHintOp2Shift = 5 , dart::kHintOp2Bits = 3 } |
enum | dart::ScaleFactor { dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
Functions | |
static Register | dart::ConcreteRegister (Register r) |
static Condition | dart::InvertCondition (Condition c) |
static uint64_t | dart::RotateRight (uint64_t value, uint8_t rotate, uint8_t width) |
static uint64_t | dart::RepeatBitsAcrossReg (uint8_t reg_size, uint64_t value, uint8_t width) |
constexpr bool | dart::operator== (Register r, LinkRegister) |
constexpr bool | dart::operator!= (Register r, LinkRegister lr) |
Register | dart::ConcreteRegister (LinkRegister) |
Variables | |
const VRegister | dart::VTMP = V31 |
const Register | dart::CALLEE_SAVED_TEMP2 = R20 |
const Register | dart::HEAP_BITS = R28 |
const Register | dart::NULL_REG = R22 |
const int | dart::kXRegSizeInBits = 64 |
const int | dart::kWRegSizeInBits = 32 |
const int64_t | dart::kXRegMask = 0xffffffffffffffffL |
const int64_t | dart::kWRegMask = 0x00000000ffffffffL |
const Register | dart::kAbiFirstPreservedCpuReg = R19 |
const Register | dart::kAbiLastPreservedCpuReg = R28 |
const Register | dart::kDartFirstVolatileCpuReg = R0 |
const Register | dart::kDartLastVolatileCpuReg = R14 |
const int | dart::kDartVolatileFpuRegCount = 24 |
#define APPLY_OP_LIST | ( | _V | ) |
Definition at line 1092 of file constants_arm64.h.
#define DART_ASSEMBLER_HAS_NULL_REG 1 |
Definition at line 158 of file constants_arm64.h.
#define IS_OP | ( | op | ) |
Definition at line 1502 of file constants_arm64.h.
#define LINK_REGISTER (LinkRegister()) |
Definition at line 1642 of file constants_arm64.h.
#define LR LR_DO_NOT_USE_DIRECTLY |
Definition at line 32 of file constants_arm64.h.
#define R | ( | reg | ) | (static_cast<RegList>(1) << (reg)) |
Definition at line 493 of file constants_arm64.h.