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constants_arm64.h File Reference
#include "platform/assert.h"
#include "platform/globals.h"
#include "platform/utils.h"
#include "vm/constants_base.h"

Go to the source code of this file.

Classes

struct  dart::SharedSlowPathStubABI
 
struct  dart::InstantiationABI
 
struct  dart::InstantiateTAVInternalRegs
 
struct  dart::TTSInternalRegs
 
struct  dart::STCInternalRegs
 
struct  dart::TypeTestABI
 
struct  dart::AssertSubtypeABI
 
struct  dart::InitStaticFieldABI
 
struct  dart::InitLateStaticFieldInternalRegs
 
struct  dart::InitInstanceFieldABI
 
struct  dart::InitLateInstanceFieldInternalRegs
 
struct  dart::LateInitializationErrorABI
 
struct  dart::ThrowABI
 
struct  dart::ReThrowABI
 
struct  dart::AssertBooleanABI
 
struct  dart::RangeErrorABI
 
struct  dart::AllocateObjectABI
 
struct  dart::AllocateClosureABI
 
struct  dart::AllocateMintABI
 
struct  dart::AllocateBoxABI
 
struct  dart::AllocateArrayABI
 
struct  dart::AllocateRecordABI
 
struct  dart::AllocateSmallRecordABI
 
struct  dart::AllocateTypedDataArrayABI
 
struct  dart::BoxDoubleStubABI
 
struct  dart::DoubleToIntegerStubABI
 
struct  dart::SuspendStubABI
 
struct  dart::InitSuspendableFunctionStubABI
 
struct  dart::ResumeStubABI
 
struct  dart::ReturnStubABI
 
struct  dart::AsyncExceptionHandlerStubABI
 
struct  dart::CloneSuspendStateStubABI
 
struct  dart::FfiAsyncCallbackSendStubABI
 
struct  dart::DispatchTableNullErrorABI
 
class  dart::CallingConventions
 
struct  dart::DartCallingConvention
 
class  dart::Instr
 
struct  dart::LinkRegister
 

Namespaces

namespace  dart
 

Macros

#define LR   LR_DO_NOT_USE_DIRECTLY
 
#define DART_ASSEMBLER_HAS_NULL_REG   1
 
#define R(reg)   (static_cast<RegList>(1) << (reg))
 
#define APPLY_OP_LIST(_V)
 
#define IS_OP(op)
 
#define LINK_REGISTER   (LinkRegister())
 

Enumerations

enum  dart::Register {
  dart::R0 = 0 , dart::R1 = 1 , dart::R2 = 2 , dart::R3 = 3 ,
  dart::R4 = 4 , dart::R5 = 5 , dart::R6 = 6 , dart::R7 = 7 ,
  dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 ,
  dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 ,
  dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::FP = R11 , dart::NOTFP = R7 ,
  dart::IP = R12 , dart::SP = R13 , dart::LR = R14 , dart::PC = R15 ,
  dart::R0 = 0 , dart::R1 = 1 , dart::R2 = 2 , dart::R3 = 3 ,
  dart::R4 = 4 , dart::R5 = 5 , dart::R6 = 6 , dart::R7 = 7 ,
  dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 ,
  dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 ,
  dart::R16 = 16 , dart::R17 = 17 , dart::R18 = 18 , dart::R19 = 19 ,
  dart::R20 = 20 , dart::R21 = 21 , dart::R22 = 22 , dart::R23 = 23 ,
  dart::R24 = 24 , dart::R25 = 25 , dart::R26 = 26 , dart::R27 = 27 ,
  dart::R28 = 28 , dart::R29 = 29 , dart::R30 = 30 , dart::R31 = 31 ,
  dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::kNoRegister2 = -2 , dart::CSP = 32 ,
  dart::ZR = 33 , dart::IP0 = R16 , dart::IP1 = R17 , dart::SP = R13 ,
  dart::FP = R11 , dart::LR = R14 , dart::EAX = 0 , dart::ECX = 1 ,
  dart::EDX = 2 , dart::EBX = 3 , dart::ESP = 4 , dart::EBP = 5 ,
  dart::ESI = 6 , dart::EDI = 7 , dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 ,
  dart::ZR = 33 , dart::RA = 1 , dart::SP = R13 , dart::GP = 3 ,
  dart::TP = 4 , dart::T0 = 5 , dart::T1 = 6 , dart::T2 = 7 ,
  dart::FP = R11 , dart::S1 = 1 , dart::A0 = 10 , dart::A1 = 11 ,
  dart::A2 = 12 , dart::A3 = 13 , dart::A4 = 14 , dart::A5 = 15 ,
  dart::A6 = 16 , dart::A7 = 17 , dart::S2 = 2 , dart::S3 = 3 ,
  dart::S4 = 4 , dart::S5 = 5 , dart::S6 = 6 , dart::S7 = 7 ,
  dart::S8 = 8 , dart::S9 = 9 , dart::S10 = 10 , dart::S11 = 11 ,
  dart::T3 = 28 , dart::T4 = 29 , dart::T5 = 30 , dart::T6 = 31 ,
  dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1 , dart::RA2 = T0 , dart::S0 = 0 ,
  dart::RAX = 0 , dart::RCX = 1 , dart::RDX = 2 , dart::RBX = 3 ,
  dart::RSP = 4 , dart::RBP = 5 , dart::RSI = 6 , dart::RDI = 7 ,
  dart::R8 = 8 , dart::R9 = 9 , dart::R10 = 10 , dart::R11 = 11 ,
  dart::R12 = 12 , dart::R13 = 13 , dart::R14 = 14 , dart::R15 = 15 ,
  dart::kNumberOfCpuRegisters = 16 , dart::kNoRegister = -1
}
 
enum  dart::VRegister {
  dart::V0 = 0 , dart::V1 = 1 , dart::V2 = 2 , dart::V3 = 3 ,
  dart::V4 = 4 , dart::V5 = 5 , dart::V6 = 6 , dart::V7 = 7 ,
  dart::V8 = 8 , dart::V9 = 9 , dart::V10 = 10 , dart::V11 = 11 ,
  dart::V12 = 12 , dart::V13 = 13 , dart::V14 = 14 , dart::V15 = 15 ,
  dart::V16 = 16 , dart::V17 = 17 , dart::V18 = 18 , dart::V19 = 19 ,
  dart::V20 = 20 , dart::V21 = 21 , dart::V22 = 22 , dart::V23 = 23 ,
  dart::V24 = 24 , dart::V25 = 25 , dart::V26 = 26 , dart::V27 = 27 ,
  dart::V28 = 28 , dart::V29 = 29 , dart::V30 = 30 , dart::V31 = 31 ,
  dart::kNumberOfVRegisters = 32 , dart::kNoVRegister = -1
}
 
enum  dart::Condition {
  dart::kNoCondition = -1 , dart::EQ = 0 , dart::NE = 1 , dart::CS = 2 ,
  dart::CC = 3 , dart::MI = 4 , dart::PL = 5 , dart::VS = 6 ,
  dart::VC = 7 , dart::HI = 8 , dart::LS = 9 , dart::GE = 10 ,
  dart::LT = 11 , dart::GT = 12 , dart::LE = 13 , dart::AL = 14 ,
  dart::kSpecialCondition = 15 , dart::kNumberOfConditions = 16 , dart::EQUAL = EQ , dart::ZERO = EQUAL ,
  dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL , dart::LESS = LT , dart::LESS_EQUAL = LE ,
  dart::GREATER_EQUAL = GE , dart::GREATER = GT , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS ,
  dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC ,
  dart::kInvalidCondition = 16 , dart::kNoCondition = -1 , dart::EQ = 0 , dart::NE = 1 ,
  dart::CS = 2 , dart::CC = 3 , dart::MI = 4 , dart::PL = 5 ,
  dart::VS = 6 , dart::VC = 7 , dart::HI = 8 , dart::LS = 9 ,
  dart::GE = 10 , dart::LT = 11 , dart::GT = 12 , dart::LE = 13 ,
  dart::AL = 14 , dart::NV = 15 , dart::kNumberOfConditions = 16 , dart::EQUAL = EQ ,
  dart::ZERO = EQUAL , dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL , dart::LESS = LT ,
  dart::LESS_EQUAL = LE , dart::GREATER_EQUAL = GE , dart::GREATER = GT , dart::UNSIGNED_LESS = CC ,
  dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS , dart::OVERFLOW = VS ,
  dart::NO_OVERFLOW = VC , dart::kInvalidCondition = 16 , dart::kNoCondition = -1 , dart::EQ = 0 ,
  dart::NE = 1 , dart::CS = 2 , dart::CC = 3 , dart::MI = 4 ,
  dart::PL = 5 , dart::VS = 6 , dart::VC = 7 , dart::HI = 8 ,
  dart::LS = 9 , dart::GE = 10 , dart::LT = 11 , dart::GT = 12 ,
  dart::LE = 13 , dart::AL = 14 , dart::NV = 15 , dart::kNumberOfConditions = 16 ,
  dart::EQUAL = EQ , dart::ZERO = EQUAL , dart::NOT_EQUAL = NE , dart::NOT_ZERO = NOT_EQUAL ,
  dart::LESS = LT , dart::LESS_EQUAL = LE , dart::GREATER_EQUAL = GE , dart::GREATER = GT ,
  dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI , dart::UNSIGNED_GREATER_EQUAL = CS ,
  dart::OVERFLOW = VS , dart::NO_OVERFLOW = VC , dart::kInvalidCondition = 16 , dart::OVERFLOW = VS ,
  dart::NO_OVERFLOW = VC , dart::BELOW = 2 , dart::ABOVE_EQUAL = 3 , dart::EQUAL = EQ ,
  dart::NOT_EQUAL = NE , dart::BELOW_EQUAL = 6 , dart::ABOVE = 7 , dart::SIGN = 8 ,
  dart::NOT_SIGN = 9 , dart::PARITY_EVEN = 10 , dart::PARITY_ODD = 11 , dart::LESS = LT ,
  dart::GREATER_EQUAL = GE , dart::LESS_EQUAL = LE , dart::GREATER = GT , dart::ZERO = EQUAL ,
  dart::NOT_ZERO = NOT_EQUAL , dart::NEGATIVE = SIGN , dart::POSITIVE = NOT_SIGN , dart::CARRY = BELOW ,
  dart::NOT_CARRY = ABOVE_EQUAL , dart::UNSIGNED_LESS = CC , dart::UNSIGNED_LESS_EQUAL = LS , dart::UNSIGNED_GREATER = HI ,
  dart::UNSIGNED_GREATER_EQUAL = CS , dart::kInvalidCondition = 16
}
 
enum  dart::Bits {
  dart::B0 = (1 << 0) , dart::B1 = (1 << 1) , dart::B2 = (1 << 2) , dart::B3 = (1 << 3) ,
  dart::B4 = (1 << 4) , dart::B5 = (1 << 5) , dart::B6 = (1 << 6) , dart::B7 = (1 << 7) ,
  dart::B8 = (1 << 8) , dart::B9 = (1 << 9) , dart::B10 = (1 << 10) , dart::B11 = (1 << 11) ,
  dart::B12 = (1 << 12) , dart::B13 = (1 << 13) , dart::B14 = (1 << 14) , dart::B15 = (1 << 15) ,
  dart::B16 = (1 << 16) , dart::B17 = (1 << 17) , dart::B18 = (1 << 18) , dart::B19 = (1 << 19) ,
  dart::B20 = (1 << 20) , dart::B21 = (1 << 21) , dart::B22 = (1 << 22) , dart::B23 = (1 << 23) ,
  dart::B24 = (1 << 24) , dart::B25 = (1 << 25) , dart::B26 = (1 << 26) , dart::B27 = (1 << 27) ,
  dart::B28 = (1 << 28) , dart::B29 = (1 << 29) , dart::B30 = (1 << 30) , dart::B31 = (1 << 31)
}
 
enum  dart::MainOp {
  dart::DPImmediateMask = 0x1c000000 , dart::DPImmediateFixed = B28 , dart::CompareBranchMask = 0x1c000000 , dart::CompareBranchFixed = B28 | B26 ,
  dart::LoadStoreMask = B27 | B25 , dart::LoadStoreFixed = B27 , dart::DPRegisterMask = 0x0e000000 , dart::DPRegisterFixed = B27 | B25 ,
  dart::DPSimd1Mask = 0x1e000000 , dart::DPSimd1Fixed = B27 | B26 | B25 , dart::DPSimd2Mask = 0x1e000000 , dart::DPSimd2Fixed = B28 | DPSimd1Fixed ,
  dart::FPMask = 0x5e000000 , dart::FPFixed = B28 | B27 | B26 | B25
}
 
enum  dart::CompareAndBranchOp { dart::CompareAndBranchMask = 0x7e000000 , dart::CompareAndBranchFixed = CompareBranchFixed | B29 , dart::CBZ = CompareAndBranchFixed , dart::CBNZ = CompareAndBranchFixed | B24 }
 
enum  dart::ConditionalBranchOp { dart::ConditionalBranchMask = 0xfe000000 , dart::ConditionalBranchFixed = CompareBranchFixed | B30 , dart::BCOND = ConditionalBranchFixed }
 
enum  dart::ExceptionGenOp {
  dart::ExceptionGenMask = 0xff000000 , dart::ExceptionGenFixed = CompareBranchFixed | B31 | B30 , dart::SVC = ExceptionGenFixed | B0 , dart::BRK = ExceptionGenFixed | B21 ,
  dart::HLT = ExceptionGenFixed | B22
}
 
enum  dart::SystemOp { dart::SystemMask = 0xffc00000 , dart::SystemFixed = CompareBranchFixed | B31 | B30 | B24 , dart::HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0 , dart::CLREX }
 
enum  dart::TestAndBranchOp { dart::TestAndBranchMask = 0x7e000000 , dart::TestAndBranchFixed = CompareBranchFixed | B29 | B25 , dart::TBZ = TestAndBranchFixed , dart::TBNZ = TestAndBranchFixed | B24 }
 
enum  dart::UnconditionalBranchOp { dart::UnconditionalBranchMask = 0x7c000000 , dart::UnconditionalBranchFixed = CompareBranchFixed , dart::B = UnconditionalBranchFixed , dart::BL = UnconditionalBranchFixed | B31 }
 
enum  dart::UnconditionalBranchRegOp {
  dart::UnconditionalBranchRegMask = 0xfe000000 , dart::UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25 , dart::BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16 , dart::BLR = BR | B21 ,
  dart::RET = BR | B22
}
 
enum  dart::LoadRegLiteralOp { dart::LoadRegLiteralMask = 0x3b000000 , dart::LoadRegLiteralFixed = LoadStoreFixed | B28 , dart::LDRpc = LoadRegLiteralFixed }
 
enum  dart::LoadStoreExclusiveOp {
  dart::LoadStoreExclusiveMask = 0x3f000000 , dart::LoadStoreExclusiveFixed = B27 , dart::LDXR = LoadStoreExclusiveFixed | B22 , dart::STXR = LoadStoreExclusiveFixed ,
  dart::LDAR = LoadStoreExclusiveFixed | B23 | B22 | B15 , dart::STLR = LoadStoreExclusiveFixed | B23 | B15
}
 
enum  dart::AtomicMemoryOp { dart::AtomicMemoryMask = 0x3f200c00 , dart::AtomicMemoryFixed = B29 | B28 | B27 | B21 , dart::LDCLR = AtomicMemoryFixed | B12 , dart::LDSET = AtomicMemoryFixed | B13 | B12 }
 
enum  dart::LoadStoreRegOp {
  dart::LoadStoreRegMask = 0x3a000000 , dart::LoadStoreRegFixed = LoadStoreFixed | B29 | B28 , dart::STR = LoadStoreRegFixed , dart::LDR = LoadStoreRegFixed | B22 ,
  dart::LDRS = LoadStoreRegFixed | B23 , dart::FSTR = STR | B26 , dart::FLDR = LDR | B26 , dart::FSTRQ = STR | B26 | B23 ,
  dart::FLDRQ = LDR | B26 | B23
}
 
enum  dart::LoadStoreRegPairOp {
  dart::LoadStoreRegPairMask = 0x3a000000 , dart::LoadStoreRegPairFixed = LoadStoreFixed | B29 , dart::STP = LoadStoreRegPairFixed , dart::LDP = LoadStoreRegPairFixed | B22 ,
  dart::FSTP = STP | B26 , dart::FLDP = LDP | B26
}
 
enum  dart::AddSubImmOp { dart::AddSubImmMask = 0x1f000000 , dart::AddSubImmFixed = DPImmediateFixed | B24 , dart::ADDI = AddSubImmFixed , dart::SUBI = AddSubImmFixed | B30 }
 
enum  dart::BitfieldOp {
  dart::BitfieldMask = 0x1f800000 , dart::BitfieldFixed = 0x13000000 , dart::SBFM = BitfieldFixed , dart::BFM = BitfieldFixed | B29 ,
  dart::UBFM = BitfieldFixed | B30 , dart::Bitfield64 = B31 | B22
}
 
enum  dart::LogicalImmOp {
  dart::LogicalImmMask = 0x1f800000 , dart::LogicalImmFixed = DPImmediateFixed | B25 , dart::ANDI = LogicalImmFixed , dart::ORRI = LogicalImmFixed | B29 ,
  dart::EORI = LogicalImmFixed | B30 , dart::ANDIS = LogicalImmFixed | B30 | B29
}
 
enum  dart::MoveWideOp {
  dart::MoveWideMask = 0x1f800000 , dart::MoveWideFixed = DPImmediateFixed | B25 | B23 , dart::MOVN = MoveWideFixed , dart::MOVZ = MoveWideFixed | B30 ,
  dart::MOVK = MoveWideFixed | B30 | B29
}
 
enum  dart::PCRelOp { dart::PCRelMask = 0x1f000000 , dart::PCRelFixed = DPImmediateFixed , dart::ADR = PCRelFixed , dart::ADRP = PCRelFixed | B31 }
 
enum  dart::AddSubShiftExtOp { dart::AddSubShiftExtMask = 0x1f000000 , dart::AddSubShiftExtFixed = DPRegisterFixed | B24 , dart::ADD = 4 , dart::SUB = 2 }
 
enum  dart::AddSubWithCarryOp { dart::AddSubWithCarryMask = 0x1fe00000 , dart::AddSubWithCarryFixed = DPRegisterFixed | B28 , dart::ADC = 5 , dart::SBC = 6 }
 
enum  dart::ConditionalSelectOp {
  dart::ConditionalSelectMask = 0x1fe00000 , dart::ConditionalSelectFixed = DPRegisterFixed | B28 | B23 , dart::CSEL = ConditionalSelectFixed , dart::CSINC = ConditionalSelectFixed | B10 ,
  dart::CSINV = ConditionalSelectFixed | B30 , dart::CSNEG = ConditionalSelectFixed | B10 | B30
}
 
enum  dart::MiscDP1SourceOp { dart::MiscDP1SourceMask = 0x5fe00000 , dart::MiscDP1SourceFixed = DPRegisterFixed | B30 | B28 | B23 | B22 , dart::CLZ = MiscDP1SourceFixed | B12 , dart::RBIT = MiscDP1SourceFixed }
 
enum  dart::MiscDP2SourceOp {
  dart::MiscDP2SourceMask = 0x5fe00000 , dart::MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22 , dart::UDIV = MiscDP2SourceFixed | B11 , dart::SDIV = MiscDP2SourceFixed | B11 | B10 ,
  dart::LSLV = MiscDP2SourceFixed | B13 , dart::LSRV = MiscDP2SourceFixed | B13 | B10 , dart::ASRV = MiscDP2SourceFixed | B13 | B11
}
 
enum  dart::MiscDP3SourceOp {
  dart::MiscDP3SourceMask = 0x1f000000 , dart::MiscDP3SourceFixed = DPRegisterFixed | B28 | B24 , dart::MADDW = MiscDP3SourceFixed , dart::MADD = MiscDP3SourceFixed | B31 ,
  dart::MSUBW = MiscDP3SourceFixed | B15 , dart::MSUB = MiscDP3SourceFixed | B31 | B15 , dart::SMULH = MiscDP3SourceFixed | B31 | B22 , dart::UMULH = MiscDP3SourceFixed | B31 | B23 | B22 ,
  dart::SMADDL = MiscDP3SourceFixed | B31 | B21 , dart::UMADDL = MiscDP3SourceFixed | B31 | B23 | B21 , dart::SMSUBL = MiscDP3SourceFixed | B31 | B21 | B15 , dart::UMSUBL = MiscDP3SourceFixed | B31 | B23 | B21 | B15
}
 
enum  dart::LogicalShiftOp {
  dart::LogicalShiftMask = 0x1f000000 , dart::LogicalShiftFixed = DPRegisterFixed , dart::AND = 0 , dart::BIC = 14 ,
  dart::ORR = 12 , dart::ORN = LogicalShiftFixed | B29 | B21 , dart::EOR = 1 , dart::EON = LogicalShiftFixed | B30 | B21 ,
  dart::ANDS = LogicalShiftFixed | B30 | B29 , dart::BICS = LogicalShiftFixed | B30 | B29 | B21
}
 
enum  dart::SIMDCopyOp {
  dart::SIMDCopyMask = 0x9fe08400 , dart::SIMDCopyFixed = DPSimd1Fixed | B10 , dart::VDUPI = SIMDCopyFixed | B30 | B11 , dart::VINSI = SIMDCopyFixed | B30 | B12 | B11 ,
  dart::VMOVW = SIMDCopyFixed | B13 | B12 | B11 , dart::VMOVX = SIMDCopyFixed | B30 | B13 | B12 | B11 , dart::VDUP = SIMDCopyFixed | B30 , dart::VINS = SIMDCopyFixed | B30 | B29
}
 
enum  dart::SIMDThreeSameOp {
  dart::SIMDThreeSameMask = 0x9f200400 , dart::SIMDThreeSameFixed = DPSimd1Fixed | B21 | B10 , dart::VAND = SIMDThreeSameFixed | B30 | B12 | B11 , dart::VORR = SIMDThreeSameFixed | B30 | B23 | B12 | B11 ,
  dart::VEOR = SIMDThreeSameFixed | B30 | B29 | B12 | B11 , dart::VADDW = SIMDThreeSameFixed | B30 | B23 | B15 , dart::VADDX = SIMDThreeSameFixed | B30 | B23 | B22 | B15 , dart::VSUBW = SIMDThreeSameFixed | B30 | B29 | B23 | B15 ,
  dart::VSUBX = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 , dart::VADDS = SIMDThreeSameFixed | B30 | B15 | B14 | B12 , dart::VADDD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B12 , dart::VSUBS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B12 ,
  dart::VSUBD = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B12 , dart::VMULS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B12 | B11 , dart::VMULD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B12 | B11 , dart::VDIVS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 | B12 | B11 ,
  dart::VDIVD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 | B12 | B11 , dart::VCEQS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 , dart::VCEQD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 , dart::VCGES = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 ,
  dart::VCGED = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 , dart::VCGTS = SIMDThreeSameFixed | B30 | B29 | B23 | B15 | B14 | B13 , dart::VCGTD = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 , dart::VMAXS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 ,
  dart::VMAXD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 | B12 , dart::VMINS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 , dart::VMIND = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VRECPSS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 | B11 ,
  dart::VRSQRTSS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 | B11
}
 
enum  dart::SIMDTwoRegOp {
  dart::SIMDTwoRegMask = 0x9f3e0c00 , dart::SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11 , dart::VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12 , dart::VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12 ,
  dart::VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12 , dart::VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12 , dart::VSQRTS = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B13 | B12 ,
  dart::VSQRTD , dart::VRECPES = SIMDTwoRegFixed | B30 | B23 | B16 | B15 | B14 | B12 , dart::VRSQRTES = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B12
}
 
enum  dart::FPCompareOp { dart::FPCompareMask = 0xffa0fc07 , dart::FPCompareFixed = FPFixed | B21 | B13 , dart::FCMPD = FPCompareFixed | B22 , dart::FCMPZD = FPCompareFixed | B22 | B3 }
 
enum  dart::FPOneSourceOp {
  dart::FPOneSourceMask = 0x5f207c00 , dart::FPOneSourceFixed = FPFixed | B21 | B14 , dart::FMOVDD = FPOneSourceFixed | B22 , dart::FABSD = FPOneSourceFixed | B22 | B15 ,
  dart::FNEGD = FPOneSourceFixed | B22 | B16 , dart::FSQRTD = FPOneSourceFixed | B22 | B16 | B15 , dart::FCVTDS = FPOneSourceFixed | B15 | B17 , dart::FCVTSD = FPOneSourceFixed | B22 | B17
}
 
enum  dart::FPTwoSourceOp {
  dart::FPTwoSourceMask = 0xff200c00 , dart::FPTwoSourceFixed = FPFixed | B21 | B11 , dart::FMULD = FPTwoSourceFixed | B22 , dart::FDIVD = FPTwoSourceFixed | B22 | B12 ,
  dart::FADDD = FPTwoSourceFixed | B22 | B13 , dart::FSUBD = FPTwoSourceFixed | B22 | B13 | B12
}
 
enum  dart::FPImmOp { dart::FPImmMask = 0x5f201c00 , dart::FPImmFixed = FPFixed | B21 | B12 , dart::FMOVSI = FPImmFixed , dart::FMOVDI = FPImmFixed | B22 }
 
enum  dart::FPIntCvtOp {
  dart::FPIntCvtMask = 0x5f00fc00 , dart::FPIntCvtFixed = FPFixed | B21 , dart::FMOVRS = FPIntCvtFixed | B18 | B17 , dart::FMOVSR = FPIntCvtFixed | B18 | B17 | B16 ,
  dart::FMOVRD = FPIntCvtFixed | B22 | B18 | B17 , dart::FMOVDR = FPIntCvtFixed | B22 | B18 | B17 | B16 , dart::FCVTZS_D = FPIntCvtFixed | B22 | B20 | B19 , dart::FCVTMS_D = FPIntCvtFixed | B22 | B20 ,
  dart::FCVTPS_D = FPIntCvtFixed | B22 | B19 , dart::SCVTFD = FPIntCvtFixed | B22 | B17
}
 
enum  dart::Shift {
  dart::kNoShift = -1 , dart::LSL = 0 , dart::LSR = 1 , dart::ASR = 2 ,
  dart::ROR = 3 , dart::kMaxShift = 4 , dart::kNoShift = -1 , dart::LSL = 0 ,
  dart::LSR = 1 , dart::ASR = 2 , dart::ROR = 3 , dart::kMaxShift = 4
}
 
enum  dart::Extend {
  dart::kNoExtend = -1 , dart::UXTB = 0 , dart::UXTH = 1 , dart::UXTW = 2 ,
  dart::UXTX = 3 , dart::SXTB = 4 , dart::SXTH = 5 , dart::SXTW = 6 ,
  dart::SXTX = 7 , dart::kMaxExtend = 8
}
 
enum  dart::R31Type { dart::R31IsSP , dart::R31IsZR }
 
enum  dart::InstructionFields {
  dart::kConditionShift = 28 , dart::kConditionBits = 4 , dart::kTypeShift = 25 , dart::kTypeBits = 3 ,
  dart::kLinkShift = 24 , dart::kLinkBits = 1 , dart::kUShift = 23 , dart::kUBits = 1 ,
  dart::kOpcodeShift = 21 , dart::kOpcodeBits = 4 , dart::kSShift = 20 , dart::kSBits = 1 ,
  dart::kRnShift = 16 , dart::kRnBits = 4 , dart::kRdShift = 12 , dart::kRdBits = 4 ,
  dart::kRsShift = 8 , dart::kRsBits = 4 , dart::kRmShift = 0 , dart::kRmBits = 4 ,
  dart::kRotateShift = 8 , dart::kRotateBits = 4 , dart::kImmed8Shift = 0 , dart::kImmed8Bits = 8 ,
  dart::kShiftImmShift = 7 , dart::kShiftRegisterShift = 8 , dart::kShiftImmBits = 5 , dart::kShiftShift = 5 ,
  dart::kShiftBits = 2 , dart::kOffset12Shift = 0 , dart::kOffset12Bits = 12 , dart::kOffset12Mask = 0x00000fff ,
  dart::kMulRdShift = 16 , dart::kMulRdBits = 4 , dart::kMulRnShift = 12 , dart::kMulRnBits = 4 ,
  dart::kLdrExRnShift = 16 , dart::kLdrExRtShift = 12 , dart::kStrExRnShift = 16 , dart::kStrExRdShift = 12 ,
  dart::kStrExRtShift = 0 , dart::kMediaOp1Shift = 20 , dart::kMediaOp1Bits = 5 , dart::kMediaOp2Shift = 5 ,
  dart::kMediaOp2Bits = 3 , dart::kDivRdShift = 16 , dart::kDivRdBits = 4 , dart::kDivRmShift = 8 ,
  dart::kDivRmBits = 4 , dart::kDivRnShift = 0 , dart::kDivRnBits = 4 , dart::kBitFieldExtractWidthShift = 16 ,
  dart::kBitFieldExtractWidthBits = 5 , dart::kBitFieldExtractLSBShift = 7 , dart::kBitFieldExtractLSBBits = 5 , dart::kBitFieldExtractRnShift = 0 ,
  dart::kBitFieldExtractRnBits = 4 , dart::kCRmShift = 0 , dart::kCRmBits = 4 , dart::kOpc2Shift = 5 ,
  dart::kOpc2Bits = 3 , dart::kCoprocShift = 8 , dart::kCoprocBits = 4 , dart::kCRnShift = 16 ,
  dart::kCRnBits = 4 , dart::kOpc1Shift = 21 , dart::kOpc1Bits = 3 , dart::kBranchOffsetMask = 0x00ffffff ,
  dart::kSShift = 20 , dart::kSBits = 1 , dart::kSFShift = 31 , dart::kSFBits = 1 ,
  dart::kSzShift = 30 , dart::kSzBits = 2 , dart::kRdShift = 12 , dart::kRdBits = 4 ,
  dart::kRnShift = 16 , dart::kRnBits = 4 , dart::kRaShift = 10 , dart::kRaBits = 5 ,
  dart::kRmShift = 0 , dart::kRmBits = 4 , dart::kRtShift = 0 , dart::kRtBits = 5 ,
  dart::kRt2Shift = 10 , dart::kRt2Bits = 5 , dart::kRsShift = 8 , dart::kRsBits = 4 ,
  dart::kVdShift = 0 , dart::kVdBits = 5 , dart::kVnShift = 5 , dart::kVnBits = 5 ,
  dart::kVmShift = 16 , dart::kVmBits = 5 , dart::kVtShift = 0 , dart::kVtBits = 5 ,
  dart::kVt2Shift = 10 , dart::kVt2Bits = 5 , dart::kImm3Shift = 10 , dart::kImm3Bits = 3 ,
  dart::kImm4Shift = 11 , dart::kImm4Bits = 4 , dart::kImm5Shift = 16 , dart::kImm5Bits = 5 ,
  dart::kImm6Shift = 10 , dart::kImm6Bits = 6 , dart::kImm7Shift = 15 , dart::kImm7Bits = 7 ,
  dart::kImm7Mask = 0x7f << kImm7Shift , dart::kImm8Shift = 13 , dart::kImm8Bits = 8 , dart::kImm9Shift = 12 ,
  dart::kImm9Bits = 9 , dart::kImm12Shift = 10 , dart::kImm12Bits = 12 , dart::kImm12Mask = 0xfff << kImm12Shift ,
  dart::kImm12ShiftShift = 22 , dart::kImm12ShiftBits = 2 , dart::kImm14Shift = 5 , dart::kImm14Bits = 14 ,
  dart::kImm14Mask = 0x3fff << kImm14Shift , dart::kImm16Shift = 5 , dart::kImm16Bits = 16 , dart::kImm16Mask = 0xffff << kImm16Shift ,
  dart::kImm19Shift = 5 , dart::kImm19Bits = 19 , dart::kImm19Mask = 0x7ffff << kImm19Shift , dart::kImm26Shift = 0 ,
  dart::kImm26Bits = 26 , dart::kImm26Mask = 0x03ffffff << kImm26Shift , dart::kCondShift = 0 , dart::kCondBits = 4 ,
  dart::kCondMask = 0xf << kCondShift , dart::kSelCondShift = 12 , dart::kSelCondBits = 4 , dart::kNShift = 22 ,
  dart::kNBits = 1 , dart::kImmRShift = 16 , dart::kImmRBits = 6 , dart::kImmSShift = 10 ,
  dart::kImmSBits = 6 , dart::kHWShift = 21 , dart::kHWBits = 2 , dart::kAddShiftExtendShift = 21 ,
  dart::kAddShiftExtendBits = 1 , dart::kShiftTypeShift = 22 , dart::kShiftTypeBits = 2 , dart::kExtendTypeShift = 13 ,
  dart::kExtendTypeBits = 3 , dart::kHintCRmShift = 8 , dart::kHintCRmBits = 4 , dart::kHintOp2Shift = 5 ,
  dart::kHintOp2Bits = 3
}
 
enum  dart::ScaleFactor {
  dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 ,
  dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 ,
  dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 ,
  dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 ,
  dart::TIMES_4 = 2 , dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE ,
  dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 ,
  dart::TIMES_8 = 3 , dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 ,
  dart::TIMES_1 = 0 , dart::TIMES_2 = 1 , dart::TIMES_4 = 2 , dart::TIMES_8 = 3 ,
  dart::TIMES_16 = 4 , dart::TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , dart::TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1
}
 

Functions

static Register dart::ConcreteRegister (Register r)
 
static Condition dart::InvertCondition (Condition c)
 
static uint64_t dart::RotateRight (uint64_t value, uint8_t rotate, uint8_t width)
 
static uint64_t dart::RepeatBitsAcrossReg (uint8_t reg_size, uint64_t value, uint8_t width)
 
constexpr bool dart::operator== (Register r, LinkRegister)
 
constexpr bool dart::operator!= (Register r, LinkRegister lr)
 
Register dart::ConcreteRegister (LinkRegister)
 

Variables

const VRegister dart::VTMP = V31
 
const Register dart::CALLEE_SAVED_TEMP2 = R20
 
const Register dart::HEAP_BITS = R28
 
const Register dart::NULL_REG = R22
 
const int dart::kXRegSizeInBits = 64
 
const int dart::kWRegSizeInBits = 32
 
const int64_t dart::kXRegMask = 0xffffffffffffffffL
 
const int64_t dart::kWRegMask = 0x00000000ffffffffL
 
const Register dart::kAbiFirstPreservedCpuReg = R19
 
const Register dart::kAbiLastPreservedCpuReg = R28
 
const Register dart::kDartFirstVolatileCpuReg = R0
 
const Register dart::kDartLastVolatileCpuReg = R14
 
const int dart::kDartVolatileFpuRegCount = 24
 

Macro Definition Documentation

◆ APPLY_OP_LIST

#define APPLY_OP_LIST (   _V)

Definition at line 1092 of file constants_arm64.h.

1132 {
1133 kNoShift = -1,
1134 LSL = 0, // Logical shift left
1135 LSR = 1, // Logical shift right
1136 ASR = 2, // Arithmetic shift right
1137 ROR = 3, // Rotate right
1138 kMaxShift = 4,
1139};
1140
1141enum Extend {
1142 kNoExtend = -1,
1143 UXTB = 0, // Zero extend byte.
1144 UXTH = 1, // Zero extend halfword (16 bits).
1145 UXTW = 2, // Zero extend word (32 bits).
1146 UXTX = 3, // Zero extend doubleword (64 bits).
1147 SXTB = 4, // Sign extend byte.
1148 SXTH = 5, // Sign extend halfword (16 bits).
1149 SXTW = 6, // Sign extend word (32 bits).
1150 SXTX = 7, // Sign extend doubleword (64 bits).
1151 kMaxExtend = 8,
1152};
1153
1154enum R31Type {
1155 R31IsSP,
1156 R31IsZR,
1157};
1158
1159// Constants used for the decoding or encoding of the individual fields of
1160// instructions. Based on the "Figure 3-1 ARM instruction set summary".
1161enum InstructionFields {
1162 // S-bit (modify condition register)
1163 kSShift = 29,
1164 kSBits = 1,
1165
1166 // sf field.
1167 kSFShift = 31,
1168 kSFBits = 1,
1169
1170 // size field,
1171 kSzShift = 30,
1172 kSzBits = 2,
1173
1174 // Registers.
1175 kRdShift = 0,
1176 kRdBits = 5,
1177 kRnShift = 5,
1178 kRnBits = 5,
1179 kRaShift = 10,
1180 kRaBits = 5,
1181 kRmShift = 16,
1182 kRmBits = 5,
1183 kRtShift = 0,
1184 kRtBits = 5,
1185 kRt2Shift = 10,
1186 kRt2Bits = 5,
1187 kRsShift = 16,
1188 kRsBits = 5,
1189
1190 // V Registers.
1191 kVdShift = 0,
1192 kVdBits = 5,
1193 kVnShift = 5,
1194 kVnBits = 5,
1195 kVmShift = 16,
1196 kVmBits = 5,
1197 kVtShift = 0,
1198 kVtBits = 5,
1199 kVt2Shift = 10,
1200 kVt2Bits = 5,
1201
1202 // Immediates.
1203 kImm3Shift = 10,
1204 kImm3Bits = 3,
1205 kImm4Shift = 11,
1206 kImm4Bits = 4,
1207 kImm5Shift = 16,
1208 kImm5Bits = 5,
1209 kImm6Shift = 10,
1210 kImm6Bits = 6,
1211 kImm7Shift = 15,
1212 kImm7Bits = 7,
1213 kImm7Mask = 0x7f << kImm7Shift,
1214 kImm8Shift = 13,
1215 kImm8Bits = 8,
1216 kImm9Shift = 12,
1217 kImm9Bits = 9,
1218 kImm12Shift = 10,
1219 kImm12Bits = 12,
1220 kImm12Mask = 0xfff << kImm12Shift,
1221 kImm12ShiftShift = 22,
1222 kImm12ShiftBits = 2,
1223 kImm14Shift = 5,
1224 kImm14Bits = 14,
1225 kImm14Mask = 0x3fff << kImm14Shift,
1226 kImm16Shift = 5,
1227 kImm16Bits = 16,
1228 kImm16Mask = 0xffff << kImm16Shift,
1229 kImm19Shift = 5,
1230 kImm19Bits = 19,
1231 kImm19Mask = 0x7ffff << kImm19Shift,
1232 kImm26Shift = 0,
1233 kImm26Bits = 26,
1234 kImm26Mask = 0x03ffffff << kImm26Shift,
1235
1236 kCondShift = 0,
1237 kCondBits = 4,
1238 kCondMask = 0xf << kCondShift,
1239
1240 kSelCondShift = 12,
1241 kSelCondBits = 4,
1242
1243 // Bitfield immediates.
1244 kNShift = 22,
1245 kNBits = 1,
1246 kImmRShift = 16,
1247 kImmRBits = 6,
1248 kImmSShift = 10,
1249 kImmSBits = 6,
1250
1251 kHWShift = 21,
1252 kHWBits = 2,
1253
1254 // Shift and Extend.
1255 kAddShiftExtendShift = 21,
1256 kAddShiftExtendBits = 1,
1257 kShiftTypeShift = 22,
1258 kShiftTypeBits = 2,
1259 kExtendTypeShift = 13,
1260 kExtendTypeBits = 3,
1261
1262 // Hint Fields.
1263 kHintCRmShift = 8,
1264 kHintCRmBits = 4,
1265 kHintOp2Shift = 5,
1266 kHintOp2Bits = 3,
1267};
1268
1269// Helper functions for decoding logical immediates.
1270static inline uint64_t RotateRight(uint64_t value,
1271 uint8_t rotate,
1272 uint8_t width) {
1273 ASSERT(width <= 64);
1274 uint8_t right = rotate & 63;
1275 uint8_t left = (width - rotate) & 63;
1276 return ((value & ((1ULL << right) - 1ULL)) << left) | (value >> right);
1277}
1278
1279static inline uint64_t RepeatBitsAcrossReg(uint8_t reg_size,
1280 uint64_t value,
1281 uint8_t width) {
1282 ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
1283 (width == 32));
1284 ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
1285 uint64_t result = value & ((1ULL << width) - 1ULL);
1286 for (unsigned i = width; i < reg_size; i *= 2) {
1287 result |= (result << i);
1288 }
1289 return result;
1290}
1291
1292enum ScaleFactor {
1293 TIMES_1 = 0,
1294 TIMES_2 = 1,
1295 TIMES_4 = 2,
1296 TIMES_8 = 3,
1297 TIMES_16 = 4,
1298// We can't include vm/compiler/runtime_api.h, so just be explicit instead
1299// of using (dart::)kWordSizeLog2.
1300#if defined(TARGET_ARCH_IS_64_BIT)
1301 // Used for Smi-boxed indices.
1302 TIMES_HALF_WORD_SIZE = kInt64SizeLog2 - 1,
1303 // Used for unboxed indices.
1304 TIMES_WORD_SIZE = kInt64SizeLog2,
1305#else
1306#error "Unexpected word size"
1307#endif
1308#if !defined(DART_COMPRESSED_POINTERS)
1309 TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE,
1310#else
1311 TIMES_COMPRESSED_WORD_SIZE = TIMES_HALF_WORD_SIZE,
1312#endif
1313 // Used for Smi-boxed indices.
1314 TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1,
1315};
1316
1317// The class Instr enables access to individual fields defined in the ARM
1318// architecture instruction set encoding as described in figure A3-1.
1319//
1320// Example: Test whether the instruction at ptr sets the condition code bits.
1321//
1322// bool InstructionSetsConditionCodes(byte* ptr) {
1323// Instr* instr = Instr::At(ptr);
1324// int type = instr->TypeField();
1325// return ((type == 0) || (type == 1)) && instr->HasS();
1326// }
1327//
1328class Instr {
1329 public:
1330 enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 };
1331
1332 enum class WideSize { k32Bits, k64Bits };
1333
1334 static constexpr int32_t kNopInstruction = HINT; // hint #0 === nop.
1335
1336 // Reserved brk and hlt instruction codes.
1337 static constexpr int32_t kBreakPointCode = 0xdeb0; // For breakpoint.
1338 static constexpr int32_t kSimulatorBreakCode =
1339 0xdeb2; // For breakpoint in sim.
1340 static constexpr int32_t kSimulatorRedirectCode = 0xca11; // For redirection.
1341
1342 // Breakpoint instruction filling assembler code buffers in debug mode.
1343 static constexpr int32_t kBreakPointInstruction = // brk(0xdeb0).
1344 BRK | (kBreakPointCode << kImm16Shift);
1345
1346 // Breakpoint instruction used by the simulator.
1347 // Should be distinct from kBreakPointInstruction and from a typical user
1348 // breakpoint inserted in generated code for debugging, e.g. brk(0).
1349 static constexpr int32_t kSimulatorBreakpointInstruction =
1350 HLT | (kSimulatorBreakCode << kImm16Shift);
1351
1352 // Runtime call redirection instruction used by the simulator.
1353 static constexpr int32_t kSimulatorRedirectInstruction =
1354 HLT | (kSimulatorRedirectCode << kImm16Shift);
1355
1356 // Read one particular bit out of the instruction bits.
1357 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
1358
1359 // Read a bit field out of the instruction bits.
1360 inline int Bits(int shift, int count) const {
1361 return (InstructionBits() >> shift) & ((1 << count) - 1);
1362 }
1363
1364 // Get the raw instruction bits.
1365 inline int32_t InstructionBits() const {
1366 return *reinterpret_cast<const int32_t*>(this);
1367 }
1368
1369 // Set the raw instruction bits to value.
1370 inline void SetInstructionBits(int32_t value) {
1371 *reinterpret_cast<int32_t*>(this) = value;
1372 }
1373
1374 inline void SetMoveWideBits(MoveWideOp op,
1375 Register rd,
1376 uint16_t imm,
1377 int hw,
1378 WideSize sz) {
1379 ASSERT((hw >= 0) && (hw <= 3));
1380 const int32_t size = (sz == WideSize::k64Bits) ? B31 : 0;
1381 SetInstructionBits(op | size | (static_cast<int32_t>(rd) << kRdShift) |
1382 (static_cast<int32_t>(hw) << kHWShift) |
1383 (static_cast<int32_t>(imm) << kImm16Shift));
1384 }
1385
1386 inline void SetUnconditionalBranchRegBits(UnconditionalBranchRegOp op,
1387 Register rn) {
1388 SetInstructionBits(op | (static_cast<int32_t>(rn) << kRnShift));
1389 }
1390
1391 inline void SetImm12Bits(int32_t orig, int32_t imm12) {
1392 ASSERT((imm12 & 0xfffff000) == 0);
1393 SetInstructionBits((orig & ~kImm12Mask) | (imm12 << kImm12Shift));
1394 }
1395
1396 inline int NField() const { return Bit(22); }
1397 inline int SField() const { return Bit(kSShift); }
1398 inline int SFField() const { return Bit(kSFShift); }
1399 inline int SzField() const { return Bits(kSzShift, kSzBits); }
1400 inline Register RdField() const {
1401 return static_cast<Register>(Bits(kRdShift, kRdBits));
1402 }
1403 inline Register RnField() const {
1404 return static_cast<Register>(Bits(kRnShift, kRnBits));
1405 }
1406 inline Register RaField() const {
1407 return static_cast<Register>(Bits(kRaShift, kRaBits));
1408 }
1409 inline Register RmField() const {
1410 return static_cast<Register>(Bits(kRmShift, kRmBits));
1411 }
1412 inline Register RtField() const {
1413 return static_cast<Register>(Bits(kRtShift, kRtBits));
1414 }
1415 inline Register Rt2Field() const {
1416 return static_cast<Register>(Bits(kRt2Shift, kRt2Bits));
1417 }
1418 inline Register RsField() const {
1419 return static_cast<Register>(Bits(kRsShift, kRsBits));
1420 }
1421
1422 inline VRegister VdField() const {
1423 return static_cast<VRegister>(Bits(kVdShift, kVdBits));
1424 }
1425 inline VRegister VnField() const {
1426 return static_cast<VRegister>(Bits(kVnShift, kVnBits));
1427 }
1428 inline VRegister VmField() const {
1429 return static_cast<VRegister>(Bits(kVmShift, kVmBits));
1430 }
1431 inline VRegister VtField() const {
1432 return static_cast<VRegister>(Bits(kVtShift, kVtBits));
1433 }
1434 inline VRegister Vt2Field() const {
1435 return static_cast<VRegister>(Bits(kVt2Shift, kVt2Bits));
1436 }
1437
1438 // Immediates
1439 inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
1440 inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
1441 inline int Imm7Field() const { return Bits(kImm7Shift, kImm7Bits); }
1442 // Sign-extended Imm7Field()
1443 inline int64_t SImm7Field() const {
1444 return (static_cast<int32_t>(Imm7Field()) << 25) >> 25;
1445 }
1446 inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
1447 inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
1448 // Sign-extended Imm9Field()
1449 inline int64_t SImm9Field() const {
1450 return (static_cast<int32_t>(Imm9Field()) << 23) >> 23;
1451 }
1452
1453 inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
1454 inline int Imm12ShiftField() const {
1455 return Bits(kImm12ShiftShift, kImm12ShiftBits);
1456 }
1457
1458 inline int Imm16Field() const { return Bits(kImm16Shift, kImm16Bits); }
1459 inline int HWField() const { return Bits(kHWShift, kHWBits); }
1460
1461 inline int ImmRField() const { return Bits(kImmRShift, kImmRBits); }
1462 inline int ImmSField() const { return Bits(kImmSShift, kImmSBits); }
1463
1464 inline int Imm14Field() const { return Bits(kImm14Shift, kImm14Bits); }
1465 inline int64_t SImm14Field() const {
1466 return (static_cast<int32_t>(Imm14Field()) << 18) >> 18;
1467 }
1468 inline int Imm19Field() const { return Bits(kImm19Shift, kImm19Bits); }
1469 inline int64_t SImm19Field() const {
1470 return (static_cast<int32_t>(Imm19Field()) << 13) >> 13;
1471 }
1472 inline int Imm26Field() const { return Bits(kImm26Shift, kImm26Bits); }
1473 inline int64_t SImm26Field() const {
1474 return (static_cast<int32_t>(Imm26Field()) << 6) >> 6;
1475 }
1476
1477 inline Condition ConditionField() const {
1478 return static_cast<Condition>(Bits(kCondShift, kCondBits));
1479 }
1480 inline Condition SelectConditionField() const {
1481 return static_cast<Condition>(Bits(kSelCondShift, kSelCondBits));
1482 }
1483
1484 // Shift and Extend.
1485 inline bool IsShift() const {
1486 return IsLogicalShiftOp() || (Bit(kAddShiftExtendShift) == 0);
1487 }
1488 inline bool IsExtend() const {
1489 return !IsLogicalShiftOp() && (Bit(kAddShiftExtendShift) == 1);
1490 }
1491 inline Shift ShiftTypeField() const {
1492 return static_cast<Shift>(Bits(kShiftTypeShift, kShiftTypeBits));
1493 }
1494 inline Extend ExtendTypeField() const {
1495 return static_cast<Extend>(Bits(kExtendTypeShift, kExtendTypeBits));
1496 }
1497 inline int ShiftAmountField() const { return Imm6Field(); }
1498 inline int ExtShiftAmountField() const { return Imm3Field(); }
1499
1500// Instruction identification.
1501#define IS_OP(op) \
1502 inline bool Is##op##Op() const { \
1503 return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask)); \
1504 }
1505 APPLY_OP_LIST(IS_OP)
1506#undef IS_OP
1507
1508 inline bool HasS() const { return (SField() == 1); }
1509
1510 // Indicate whether Rd can be the CSP or ZR. This does not check that the
1511 // instruction actually has an Rd field.
1512 R31Type RdMode() const {
1513 // The following instructions use CSP as Rd:
1514 // Add/sub (immediate) when not setting the flags.
1515 // Add/sub (extended) when not setting the flags.
1516 // Logical (immediate) when not setting the flags.
1517 // Otherwise, R31 is the ZR.
1518 if (IsAddSubImmOp() || (IsAddSubShiftExtOp() && IsExtend())) {
1519 if (HasS()) {
1520 return R31IsZR;
1521 } else {
1522 return R31IsSP;
1523 }
1524 }
1525 if (IsLogicalImmOp()) {
1526 const int op = Bits(29, 2);
1527 const bool set_flags = op == 3;
1528 if (set_flags) {
1529 return R31IsZR;
1530 } else {
1531 return R31IsSP;
1532 }
1533 }
1534 return R31IsZR;
1535 }
1536
1537 // Indicate whether Rn can be CSP or ZR. This does not check that the
1538 // instruction actually has an Rn field.
1539 R31Type RnMode() const {
1540 // The following instructions use CSP as Rn:
1541 // All loads and stores.
1542 // Add/sub (immediate).
1543 // Add/sub (extended).
1544 // Otherwise, r31 is ZR.
1545 if (IsLoadStoreOp() || IsAddSubImmOp() ||
1546 (IsAddSubShiftExtOp() && IsExtend())) {
1547 return R31IsSP;
1548 }
1549 return R31IsZR;
1550 }
1551
1552 // Logical immediates can't encode zero, so a return value of zero is used to
1553 // indicate a failure case. Specifically, where the constraints on imm_s are
1554 // not met.
1555 uint64_t ImmLogical() {
1556 const uint8_t reg_size = SFField() == 1 ? kXRegSizeInBits : kWRegSizeInBits;
1557 const int64_t n = NField();
1558 const int64_t imm_s = ImmSField();
1559 const int64_t imm_r = ImmRField();
1560
1561 // An integer is constructed from the n, imm_s and imm_r bits according to
1562 // the following table:
1563 //
1564 // N imms immr size S R
1565 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
1566 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
1567 // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
1568 // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
1569 // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
1570 // 0 11110s xxxxxr 2 UInt(s) UInt(r)
1571 // (s bits must not be all set)
1572 //
1573 // A pattern is constructed of size bits, where the least significant S+1
1574 // bits are set. The pattern is rotated right by R, and repeated across a
1575 // 32 or 64-bit value, depending on destination register width.
1576
1577 if (n == 1) {
1578 if (imm_s == 0x3F) {
1579 return 0;
1580 }
1581 uint64_t bits = (1ULL << (imm_s + 1)) - 1;
1582 return RotateRight(bits, imm_r, 64);
1583 } else {
1584 if ((imm_s >> 1) == 0x1F) {
1585 return 0;
1586 }
1587 for (int width = 0x20; width >= 0x2; width >>= 1) {
1588 if ((imm_s & width) == 0) {
1589 int mask = width - 1;
1590 if ((imm_s & mask) == mask) {
1591 return 0;
1592 }
1593 uint64_t bits = (1ULL << ((imm_s & mask) + 1)) - 1;
1594 return RepeatBitsAcrossReg(
1595 reg_size, RotateRight(bits, imm_r & mask, width), width);
1596 }
1597 }
1598 }
1599 UNREACHABLE();
1600 return 0;
1601 }
1602
1603 static int64_t VFPExpandImm(uint8_t imm8) {
1604 const int64_t sign = static_cast<int64_t>((imm8 & 0x80) >> 7) << 63;
1605 const int64_t hi_exp = static_cast<int64_t>(!((imm8 & 0x40) >> 6)) << 62;
1606 const int64_t mid_exp = (((imm8 & 0x40) >> 6) == 0) ? 0 : (0xffLL << 54);
1607 const int64_t low_exp = static_cast<int64_t>((imm8 & 0x30) >> 4) << 52;
1608 const int64_t frac = static_cast<int64_t>(imm8 & 0x0f) << 48;
1609 return sign | hi_exp | mid_exp | low_exp | frac;
1610 }
1611
1612 // Instructions are read out of a code stream. The only way to get a
1613 // reference to an instruction is to convert a pointer. There is no way
1614 // to allocate or create instances of class Instr.
1615 // Use the At(pc) function to create references to Instr.
1616 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
1617
1618 private:
1619 DISALLOW_ALLOCATION();
1620 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
1621};
1622
1623const uint64_t kBreakInstructionFiller = 0xD4200000D4200000L; // brk #0; brk #0
1624
1625struct LinkRegister {};
1626
1627constexpr bool operator==(Register r, LinkRegister) {
1628 return r == LR;
1629}
1630
1631constexpr bool operator!=(Register r, LinkRegister lr) {
1632 return !(r == lr);
1633}
1634
1635inline Register ConcreteRegister(LinkRegister) {
1636 return LR;
1637}
1638
1639#undef LR
1640
1641#define LINK_REGISTER (LinkRegister())
1642
1643// There are many different ARM64 CPUs out there with different alignment
1644// requirements which are mostly not very well documented.
1645//
1646// Apple Silicon CPU Optimization Guide explicitly discourages alignment of
1647// branch targets (see section 4.4.3).
1648//
1649// Aligning to 32 seems like a safe bet based on LLVM's implementation:
1650//
1651// https://github.com/llvm/llvm-project/blob/05c1447b3eabe9cc4a27866094e46c57350c5d5a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp#L107
1652//
1653#if defined(DART_TARGET_OS_MACOS_IOS) || defined(DART_TARGET_OS_MACOS)
1654const intptr_t kPreferredLoopAlignment = 1;
1655#else
1656const intptr_t kPreferredLoopAlignment = 32;
1657#endif
1658
1659} // namespace dart
1660
1661#endif // RUNTIME_VM_CONSTANTS_ARM64_H_
count
int count
Definition FontMgrTest.cpp:50
rotate
static bool rotate(const SkDCubic &cubic, int zero, int index, SkDCubic &rotPath)
Definition SkOpCubicHull.cpp:14
sign
static int sign(SkScalar x)
Definition SkPath.cpp:2141
left
static bool left(const SkPoint &p0, const SkPoint &p1)
Definition SkPolyUtils.cpp:527
right
static bool right(const SkPoint &p0, const SkPoint &p1)
Definition SkPolyUtils.cpp:532
operator!=
bool operator!=(const sk_sp< T > &a, const sk_sp< U > &b)
Definition SkRefCnt.h:355
UNREACHABLE
#define UNREACHABLE()
Definition assert.h:248
LR
#define LR
Definition constants_arm64.h:32
APPLY_OP_LIST
#define APPLY_OP_LIST(_V)
Definition constants_arm64.h:1092
IS_OP
#define IS_OP(op)
Definition constants_arm64.h:1502
operator==
bool operator==(const FlutterPoint &a, const FlutterPoint &b)
Definition embedder_assertions.h:23
ASSERT
#define ASSERT(E)
Definition entrypoints_verification_test.cc:25
value
uint8_t value
Definition fl_standard_message_codec.cc:36
result
GAsyncResult * result
Definition fl_text_input_plugin.cc:106
dart::kXRegSizeInBits
const int kXRegSizeInBits
Definition constants_arm64.h:480
dart::TIMES_COMPRESSED_HALF_WORD_SIZE
@ TIMES_COMPRESSED_HALF_WORD_SIZE
Definition constants_arm.h:965
dart::TIMES_COMPRESSED_WORD_SIZE
@ TIMES_COMPRESSED_WORD_SIZE
Definition constants_arm.h:960
dart::RotateRight
static uint64_t RotateRight(uint64_t value, uint8_t rotate, uint8_t width)
Definition constants_arm64.h:1271
dart::ConcreteRegister
Register ConcreteRegister(LinkRegister)
Definition constants_arm.h:1332
dart::kBreakInstructionFiller
constexpr uword kBreakInstructionFiller
Definition constants_arm.h:1317
dart::InstructionFields
InstructionFields
Definition constants_arm.h:853
dart::kAddShiftExtendBits
@ kAddShiftExtendBits
Definition constants_arm64.h:1257
dart::kAddShiftExtendShift
@ kAddShiftExtendShift
Definition constants_arm64.h:1256
dart::kInt64SizeLog2
constexpr intptr_t kInt64SizeLog2
Definition globals.h:452
dart::kWRegSizeInBits
const int kWRegSizeInBits
Definition constants_arm64.h:481
dart::kPreferredLoopAlignment
const intptr_t kPreferredLoopAlignment
Definition constants_arm.h:1341
dart::RepeatBitsAcrossReg
static uint64_t RepeatBitsAcrossReg(uint8_t reg_size, uint64_t value, uint8_t width)
Definition constants_arm64.h:1280
flutter::size
it will be possible to load the file into Perfetto s trace viewer disable asset Prevents usage of any non test fonts unless they were explicitly Loaded via prefetched default font Indicates whether the embedding started a prefetch of the default font manager before creating the engine run In non interactive keep the shell running after the Dart script has completed enable serial On low power devices with low core running concurrent GC tasks on threads can cause them to contend with the UI thread which could potentially lead to jank This option turns off all concurrent GC activities domain network JSON encoded network policy per domain This overrides the DisallowInsecureConnections switch Embedder can specify whether to allow or disallow insecure connections at a domain level old gen heap size
Definition switches.h:259
skcms_private::bits
uint32_t bits
Definition skcms_Transform.h:119
DISALLOW_IMPLICIT_CONSTRUCTORS
#define DISALLOW_IMPLICIT_CONSTRUCTORS(TypeName)
Definition globals.h:593
DISALLOW_ALLOCATION
#define DISALLOW_ALLOCATION()
Definition globals.h:604
width
int32_t width
Definition serialization_callbacks.cc:0

◆ DART_ASSEMBLER_HAS_NULL_REG

#define DART_ASSEMBLER_HAS_NULL_REG   1

Definition at line 158 of file constants_arm64.h.

◆ IS_OP

#define IS_OP (   op)
Value:
inline bool Is##op##Op() const { \
return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask)); \
}

Definition at line 1502 of file constants_arm64.h.

1503 { \
1504 return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask)); \
1505 }

◆ LINK_REGISTER

#define LINK_REGISTER   (LinkRegister())

Definition at line 1642 of file constants_arm64.h.

◆ LR

#define LR   LR_DO_NOT_USE_DIRECTLY

Definition at line 32 of file constants_arm64.h.

◆ R

#define R (   reg)    (static_cast<RegList>(1) << (reg))

Definition at line 493 of file constants_arm64.h.

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