Flutter Engine
The Flutter Engine
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Namespaces | |
namespace | bin |
namespace | compiler |
namespace | elf |
namespace | embedder |
namespace | internal |
namespace | kernel |
namespace | mach_o |
namespace | observatory |
namespace | pe |
namespace | snapshot_analyzer |
Enumerations | |
enum | { kPathsUriOffset = 0 , kPathsSourceOffset = 1 , kPathsEntryLength = 2 } |
enum | ClassId : intptr_t { kIllegalCid = 0 , kNativePointer , kFreeListElement , kForwardingCorpse , kByteDataViewCid , kUnmodifiableByteDataViewCid , kByteBufferCid , kNullCid , kDynamicCid , kVoidCid , kNeverCid , kNumPredefinedCids } |
enum class | CodeEntryKind { kNormal , kUnchecked , kMonomorphic , kMonomorphicUnchecked } |
enum | TypeCheckMode { kTypeCheckFromLazySpecializeStub , kTypeCheckFromSlowStub , kTypeCheckFromInline } |
enum | BlockAddressMode { DA = (0 | 0 | 0) << 21 , IA = (0 | 4 | 0) << 21 , DB = (8 | 0 | 0) << 21 , IB = (8 | 4 | 0) << 21 , DA_W = (0 | 0 | 1) << 21 , IA_W = (0 | 4 | 1) << 21 , DB_W = (8 | 0 | 1) << 21 , IB_W = (8 | 4 | 1) << 21 } |
enum class | InnerPointerAccess { kNotUntagged , kMayBeInnerPointer , kCannotBeInnerPointer } |
enum | StoreBarrierType { kNoStoreBarrier , kEmitStoreBarrier } |
enum | AlignmentType { kUnalignedAccess , kAlignedAccess } |
enum | TypeDataField { TypedDataBase_length , TypedDataView_offset_in_bytes , TypedDataView_typed_data } |
enum class | TestIntVariant { kTestBranch , kTestValue } |
enum | MatchOpCode { kMatchAndMoveBranchTrue , kMatchAndMoveBranchFalse , kNop , kMoveAny , kMoveParallelMoves , kMoveGlob , kMoveDebugStepChecks , kInvalidMatchOpCode } |
enum class | ParallelMovesHandling { kDefault , kSkip } |
enum | Representation { kNumRepresentations } |
enum | CSEMode { kOptimizeLoads , kOptimizeStores } |
enum | NativeSlotsEnumeration { kNativeSlotsCount } |
enum class | CompilerTracing { kOn , kOff } |
enum | DeoptStubKind { kLazyDeoptFromReturn , kLazyDeoptFromThrow , kEagerDeopt } |
enum | Register { R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , FP = R11 , NOTFP = R7 , IP = R12 , SP = R13 , LR = R14 , PC = R15 , R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , R16 = 16 , R17 = 17 , R18 = 18 , R19 = 19 , R20 = 20 , R21 = 21 , R22 = 22 , R23 = 23 , R24 = 24 , R25 = 25 , R26 = 26 , R27 = 27 , R28 = 28 , R29 = 29 , R30 = 30 , R31 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , kNoRegister2 = -2 , CSP = 32 , ZR = 33 , IP0 = R16 , IP1 = R17 , SP = R13 , FP = R11 , LR = R14 , EAX = 0 , ECX = 1 , EDX = 2 , EBX = 3 , ESP = 4 , EBP = 5 , ESI = 6 , EDI = 7 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , ZR = 33 , RA = 1 , SP = R13 , GP = 3 , TP = 4 , T0 = 5 , T1 = 6 , T2 = 7 , FP = R11 , S1 = 1 , A0 = 10 , A1 = 11 , A2 = 12 , A3 = 13 , A4 = 14 , A5 = 15 , A6 = 16 , A7 = 17 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , T3 = 28 , T4 = 29 , T5 = 30 , T6 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , RA2 = T0 , S0 = 0 , RAX = 0 , RCX = 1 , RDX = 2 , RBX = 3 , RSP = 4 , RBP = 5 , RSI = 6 , RDI = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 } |
enum | SRegister { kNoSRegister = -1 , S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , S12 = 12 , S13 = 13 , S14 = 14 , S15 = 15 , S16 = 16 , S17 = 17 , S18 = 18 , S19 = 19 , S20 = 20 , S21 = 21 , S22 = 22 , S23 = 23 , S24 = 24 , S25 = 25 , S26 = 26 , S27 = 27 , S28 = 28 , S29 = 29 , S30 = 30 , S31 = 31 , kNumberOfSRegisters = 32 } |
enum | DRegister { kNoDRegister = -1 , D0 = 0 , D1 = 1 , D2 = 2 , D3 = 3 , D4 = 4 , D5 = 5 , D6 = 6 , D7 = 7 , D8 = 8 , D9 = 9 , D10 = 10 , D11 = 11 , D12 = 12 , D13 = 13 , D14 = 14 , D15 = 15 , D16 = 16 , D17 = 17 , D18 = 18 , D19 = 19 , D20 = 20 , D21 = 21 , D22 = 22 , D23 = 23 , D24 = 24 , D25 = 25 , D26 = 26 , D27 = 27 , D28 = 28 , D29 = 29 , D30 = 30 , D31 = 31 , kNumberOfDRegisters = 32 , kNumberOfOverlappingDRegisters = 16 } |
enum | QRegister { kNoQRegister = -1 , Q0 = 0 , Q1 = 1 , Q2 = 2 , Q3 = 3 , Q4 = 4 , Q5 = 5 , Q6 = 6 , Q7 = 7 , Q8 = 8 , Q9 = 9 , Q10 = 10 , Q11 = 11 , Q12 = 12 , Q13 = 13 , Q14 = 14 , Q15 = 15 , kNumberOfQRegisters = 16 , kNumberOfOverlappingQRegisters = 8 } |
enum | Condition { kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , kSpecialCondition = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , OVERFLOW = VS , NO_OVERFLOW = VC , BELOW = 2 , ABOVE_EQUAL = 3 , EQUAL = EQ , NOT_EQUAL = NE , BELOW_EQUAL = 6 , ABOVE = 7 , SIGN = 8 , NOT_SIGN = 9 , PARITY_EVEN = 10 , PARITY_ODD = 11 , LESS = LT , GREATER_EQUAL = GE , LESS_EQUAL = LE , GREATER = GT , ZERO = EQUAL , NOT_ZERO = NOT_EQUAL , NEGATIVE = SIGN , POSITIVE = NOT_SIGN , CARRY = BELOW , NOT_CARRY = ABOVE_EQUAL , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , kInvalidCondition = 16 } |
enum | Opcode { kNoOperand = -1 , AND = 0 , EOR = 1 , SUB = 2 , RSB = 3 , ADD = 4 , ADC = 5 , SBC = 6 , RSC = 7 , TST = 8 , TEQ = 9 , CMP = 10 , CMN = 11 , ORR = 12 , MOV = 13 , BIC = 14 , MVN = 15 , kMaxOperand = 16 , LUI = 0b0110111 , AUIPC = 0b0010111 , JAL = 0b1101111 , JALR = 0b1100111 , BRANCH = 0b1100011 , LOAD = 0b0000011 , STORE = 0b0100011 , OPIMM = 0b0010011 , OP = 0b0110011 , MISCMEM = 0b0001111 , SYSTEM = 0b1110011 , OP32 = 0b0111011 , OPIMM32 = 0b0011011 , AMO = 0b0101111 , LOADFP = 0b0000111 , STOREFP = 0b0100111 , FMADD = 0b1000011 , FMSUB = 0b1000111 , FNMSUB = 0b1001011 , FNMADD = 0b1001111 , OPFP = 0b1010011 } |
enum | Shift { kNoShift = -1 , LSL = 0 , LSR = 1 , ASR = 2 , ROR = 3 , kMaxShift = 4 , kNoShift = -1 , LSL = 0 , LSR = 1 , ASR = 2 , ROR = 3 , kMaxShift = 4 } |
enum | InstructionFields { kConditionShift = 28 , kConditionBits = 4 , kTypeShift = 25 , kTypeBits = 3 , kLinkShift = 24 , kLinkBits = 1 , kUShift = 23 , kUBits = 1 , kOpcodeShift = 21 , kOpcodeBits = 4 , kSShift = 20 , kSBits = 1 , kRnShift = 16 , kRnBits = 4 , kRdShift = 12 , kRdBits = 4 , kRsShift = 8 , kRsBits = 4 , kRmShift = 0 , kRmBits = 4 , kRotateShift = 8 , kRotateBits = 4 , kImmed8Shift = 0 , kImmed8Bits = 8 , kShiftImmShift = 7 , kShiftRegisterShift = 8 , kShiftImmBits = 5 , kShiftShift = 5 , kShiftBits = 2 , kOffset12Shift = 0 , kOffset12Bits = 12 , kOffset12Mask = 0x00000fff , kMulRdShift = 16 , kMulRdBits = 4 , kMulRnShift = 12 , kMulRnBits = 4 , kLdrExRnShift = 16 , kLdrExRtShift = 12 , kStrExRnShift = 16 , kStrExRdShift = 12 , kStrExRtShift = 0 , kMediaOp1Shift = 20 , kMediaOp1Bits = 5 , kMediaOp2Shift = 5 , kMediaOp2Bits = 3 , kDivRdShift = 16 , kDivRdBits = 4 , kDivRmShift = 8 , kDivRmBits = 4 , kDivRnShift = 0 , kDivRnBits = 4 , kBitFieldExtractWidthShift = 16 , kBitFieldExtractWidthBits = 5 , kBitFieldExtractLSBShift = 7 , kBitFieldExtractLSBBits = 5 , kBitFieldExtractRnShift = 0 , kBitFieldExtractRnBits = 4 , kCRmShift = 0 , kCRmBits = 4 , kOpc2Shift = 5 , kOpc2Bits = 3 , kCoprocShift = 8 , kCoprocBits = 4 , kCRnShift = 16 , kCRnBits = 4 , kOpc1Shift = 21 , kOpc1Bits = 3 , kBranchOffsetMask = 0x00ffffff , kSShift = 20 , kSBits = 1 , kSFShift = 31 , kSFBits = 1 , kSzShift = 30 , kSzBits = 2 , kRdShift = 12 , kRdBits = 4 , kRnShift = 16 , kRnBits = 4 , kRaShift = 10 , kRaBits = 5 , kRmShift = 0 , kRmBits = 4 , kRtShift = 0 , kRtBits = 5 , kRt2Shift = 10 , kRt2Bits = 5 , kRsShift = 8 , kRsBits = 4 , kVdShift = 0 , kVdBits = 5 , kVnShift = 5 , kVnBits = 5 , kVmShift = 16 , kVmBits = 5 , kVtShift = 0 , kVtBits = 5 , kVt2Shift = 10 , kVt2Bits = 5 , kImm3Shift = 10 , kImm3Bits = 3 , kImm4Shift = 11 , kImm4Bits = 4 , kImm5Shift = 16 , kImm5Bits = 5 , kImm6Shift = 10 , kImm6Bits = 6 , kImm7Shift = 15 , kImm7Bits = 7 , kImm7Mask = 0x7f << kImm7Shift , kImm8Shift = 13 , kImm8Bits = 8 , kImm9Shift = 12 , kImm9Bits = 9 , kImm12Shift = 10 , kImm12Bits = 12 , kImm12Mask = 0xfff << kImm12Shift , kImm12ShiftShift = 22 , kImm12ShiftBits = 2 , kImm14Shift = 5 , kImm14Bits = 14 , kImm14Mask = 0x3fff << kImm14Shift , kImm16Shift = 5 , kImm16Bits = 16 , kImm16Mask = 0xffff << kImm16Shift , kImm19Shift = 5 , kImm19Bits = 19 , kImm19Mask = 0x7ffff << kImm19Shift , kImm26Shift = 0 , kImm26Bits = 26 , kImm26Mask = 0x03ffffff << kImm26Shift , kCondShift = 0 , kCondBits = 4 , kCondMask = 0xf << kCondShift , kSelCondShift = 12 , kSelCondBits = 4 , kNShift = 22 , kNBits = 1 , kImmRShift = 16 , kImmRBits = 6 , kImmSShift = 10 , kImmSBits = 6 , kHWShift = 21 , kHWBits = 2 , kAddShiftExtendShift = 21 , kAddShiftExtendBits = 1 , kShiftTypeShift = 22 , kShiftTypeBits = 2 , kExtendTypeShift = 13 , kExtendTypeBits = 3 , kHintCRmShift = 8 , kHintCRmBits = 4 , kHintOp2Shift = 5 , kHintOp2Bits = 3 } |
enum | ScaleFactor { TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
enum | Register { R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , FP = R11 , NOTFP = R7 , IP = R12 , SP = R13 , LR = R14 , PC = R15 , R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , R16 = 16 , R17 = 17 , R18 = 18 , R19 = 19 , R20 = 20 , R21 = 21 , R22 = 22 , R23 = 23 , R24 = 24 , R25 = 25 , R26 = 26 , R27 = 27 , R28 = 28 , R29 = 29 , R30 = 30 , R31 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , kNoRegister2 = -2 , CSP = 32 , ZR = 33 , IP0 = R16 , IP1 = R17 , SP = R13 , FP = R11 , LR = R14 , EAX = 0 , ECX = 1 , EDX = 2 , EBX = 3 , ESP = 4 , EBP = 5 , ESI = 6 , EDI = 7 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , ZR = 33 , RA = 1 , SP = R13 , GP = 3 , TP = 4 , T0 = 5 , T1 = 6 , T2 = 7 , FP = R11 , S1 = 1 , A0 = 10 , A1 = 11 , A2 = 12 , A3 = 13 , A4 = 14 , A5 = 15 , A6 = 16 , A7 = 17 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , T3 = 28 , T4 = 29 , T5 = 30 , T6 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , RA2 = T0 , S0 = 0 , RAX = 0 , RCX = 1 , RDX = 2 , RBX = 3 , RSP = 4 , RBP = 5 , RSI = 6 , RDI = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 } |
enum | VRegister { V0 = 0 , V1 = 1 , V2 = 2 , V3 = 3 , V4 = 4 , V5 = 5 , V6 = 6 , V7 = 7 , V8 = 8 , V9 = 9 , V10 = 10 , V11 = 11 , V12 = 12 , V13 = 13 , V14 = 14 , V15 = 15 , V16 = 16 , V17 = 17 , V18 = 18 , V19 = 19 , V20 = 20 , V21 = 21 , V22 = 22 , V23 = 23 , V24 = 24 , V25 = 25 , V26 = 26 , V27 = 27 , V28 = 28 , V29 = 29 , V30 = 30 , V31 = 31 , kNumberOfVRegisters = 32 , kNoVRegister = -1 } |
enum | Condition { kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , kSpecialCondition = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , OVERFLOW = VS , NO_OVERFLOW = VC , BELOW = 2 , ABOVE_EQUAL = 3 , EQUAL = EQ , NOT_EQUAL = NE , BELOW_EQUAL = 6 , ABOVE = 7 , SIGN = 8 , NOT_SIGN = 9 , PARITY_EVEN = 10 , PARITY_ODD = 11 , LESS = LT , GREATER_EQUAL = GE , LESS_EQUAL = LE , GREATER = GT , ZERO = EQUAL , NOT_ZERO = NOT_EQUAL , NEGATIVE = SIGN , POSITIVE = NOT_SIGN , CARRY = BELOW , NOT_CARRY = ABOVE_EQUAL , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , kInvalidCondition = 16 } |
enum | Bits { B0 = (1 << 0) , B1 = (1 << 1) , B2 = (1 << 2) , B3 = (1 << 3) , B4 = (1 << 4) , B5 = (1 << 5) , B6 = (1 << 6) , B7 = (1 << 7) , B8 = (1 << 8) , B9 = (1 << 9) , B10 = (1 << 10) , B11 = (1 << 11) , B12 = (1 << 12) , B13 = (1 << 13) , B14 = (1 << 14) , B15 = (1 << 15) , B16 = (1 << 16) , B17 = (1 << 17) , B18 = (1 << 18) , B19 = (1 << 19) , B20 = (1 << 20) , B21 = (1 << 21) , B22 = (1 << 22) , B23 = (1 << 23) , B24 = (1 << 24) , B25 = (1 << 25) , B26 = (1 << 26) , B27 = (1 << 27) , B28 = (1 << 28) , B29 = (1 << 29) , B30 = (1 << 30) , B31 = (1 << 31) } |
enum | MainOp { DPImmediateMask = 0x1c000000 , DPImmediateFixed = B28 , CompareBranchMask = 0x1c000000 , CompareBranchFixed = B28 | B26 , LoadStoreMask = B27 | B25 , LoadStoreFixed = B27 , DPRegisterMask = 0x0e000000 , DPRegisterFixed = B27 | B25 , DPSimd1Mask = 0x1e000000 , DPSimd1Fixed = B27 | B26 | B25 , DPSimd2Mask = 0x1e000000 , DPSimd2Fixed = B28 | DPSimd1Fixed , FPMask = 0x5e000000 , FPFixed = B28 | B27 | B26 | B25 } |
enum | CompareAndBranchOp { CompareAndBranchMask = 0x7e000000 , CompareAndBranchFixed = CompareBranchFixed | B29 , CBZ = CompareAndBranchFixed , CBNZ = CompareAndBranchFixed | B24 } |
enum | ConditionalBranchOp { ConditionalBranchMask = 0xfe000000 , ConditionalBranchFixed = CompareBranchFixed | B30 , BCOND = ConditionalBranchFixed } |
enum | ExceptionGenOp { ExceptionGenMask = 0xff000000 , ExceptionGenFixed = CompareBranchFixed | B31 | B30 , SVC = ExceptionGenFixed | B0 , BRK = ExceptionGenFixed | B21 , HLT = ExceptionGenFixed | B22 } |
enum | SystemOp { SystemMask = 0xffc00000 , SystemFixed = CompareBranchFixed | B31 | B30 | B24 , HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0 , CLREX } |
enum | TestAndBranchOp { TestAndBranchMask = 0x7e000000 , TestAndBranchFixed = CompareBranchFixed | B29 | B25 , TBZ = TestAndBranchFixed , TBNZ = TestAndBranchFixed | B24 } |
enum | UnconditionalBranchOp { UnconditionalBranchMask = 0x7c000000 , UnconditionalBranchFixed = CompareBranchFixed , B = UnconditionalBranchFixed , BL = UnconditionalBranchFixed | B31 } |
enum | UnconditionalBranchRegOp { UnconditionalBranchRegMask = 0xfe000000 , UnconditionalBranchRegFixed = CompareBranchFixed | B31 | B30 | B25 , BR = UnconditionalBranchRegFixed | B20 | B19 | B18 | B17 | B16 , BLR = BR | B21 , RET = BR | B22 } |
enum | LoadRegLiteralOp { LoadRegLiteralMask = 0x3b000000 , LoadRegLiteralFixed = LoadStoreFixed | B28 , LDRpc = LoadRegLiteralFixed } |
enum | LoadStoreExclusiveOp { LoadStoreExclusiveMask = 0x3f000000 , LoadStoreExclusiveFixed = B27 , LDXR = LoadStoreExclusiveFixed | B22 , STXR = LoadStoreExclusiveFixed , LDAR = LoadStoreExclusiveFixed | B23 | B22 | B15 , STLR = LoadStoreExclusiveFixed | B23 | B15 } |
enum | AtomicMemoryOp { AtomicMemoryMask = 0x3f200c00 , AtomicMemoryFixed = B29 | B28 | B27 | B21 , LDCLR = AtomicMemoryFixed | B12 , LDSET = AtomicMemoryFixed | B13 | B12 } |
enum | LoadStoreRegOp { LoadStoreRegMask = 0x3a000000 , LoadStoreRegFixed = LoadStoreFixed | B29 | B28 , STR = LoadStoreRegFixed , LDR = LoadStoreRegFixed | B22 , LDRS = LoadStoreRegFixed | B23 , FSTR = STR | B26 , FLDR = LDR | B26 , FSTRQ = STR | B26 | B23 , FLDRQ = LDR | B26 | B23 } |
enum | LoadStoreRegPairOp { LoadStoreRegPairMask = 0x3a000000 , LoadStoreRegPairFixed = LoadStoreFixed | B29 , STP = LoadStoreRegPairFixed , LDP = LoadStoreRegPairFixed | B22 , FSTP = STP | B26 , FLDP = LDP | B26 } |
enum | AddSubImmOp { AddSubImmMask = 0x1f000000 , AddSubImmFixed = DPImmediateFixed | B24 , ADDI = AddSubImmFixed , SUBI = AddSubImmFixed | B30 } |
enum | BitfieldOp { BitfieldMask = 0x1f800000 , BitfieldFixed = 0x13000000 , SBFM = BitfieldFixed , BFM = BitfieldFixed | B29 , UBFM = BitfieldFixed | B30 , Bitfield64 = B31 | B22 } |
enum | LogicalImmOp { LogicalImmMask = 0x1f800000 , LogicalImmFixed = DPImmediateFixed | B25 , ANDI = LogicalImmFixed , ORRI = LogicalImmFixed | B29 , EORI = LogicalImmFixed | B30 , ANDIS = LogicalImmFixed | B30 | B29 } |
enum | MoveWideOp { MoveWideMask = 0x1f800000 , MoveWideFixed = DPImmediateFixed | B25 | B23 , MOVN = MoveWideFixed , MOVZ = MoveWideFixed | B30 , MOVK = MoveWideFixed | B30 | B29 } |
enum | PCRelOp { PCRelMask = 0x1f000000 , PCRelFixed = DPImmediateFixed , ADR = PCRelFixed , ADRP = PCRelFixed | B31 } |
enum | AddSubShiftExtOp { AddSubShiftExtMask = 0x1f000000 , AddSubShiftExtFixed = DPRegisterFixed | B24 , ADD = 4 , SUB = 2 } |
enum | AddSubWithCarryOp { AddSubWithCarryMask = 0x1fe00000 , AddSubWithCarryFixed = DPRegisterFixed | B28 , ADC = 5 , SBC = 6 } |
enum | ConditionalSelectOp { ConditionalSelectMask = 0x1fe00000 , ConditionalSelectFixed = DPRegisterFixed | B28 | B23 , CSEL = ConditionalSelectFixed , CSINC = ConditionalSelectFixed | B10 , CSINV = ConditionalSelectFixed | B30 , CSNEG = ConditionalSelectFixed | B10 | B30 } |
enum | MiscDP1SourceOp { MiscDP1SourceMask = 0x5fe00000 , MiscDP1SourceFixed = DPRegisterFixed | B30 | B28 | B23 | B22 , CLZ = MiscDP1SourceFixed | B12 , RBIT = MiscDP1SourceFixed } |
enum | MiscDP2SourceOp { MiscDP2SourceMask = 0x5fe00000 , MiscDP2SourceFixed = DPRegisterFixed | B28 | B23 | B22 , UDIV = MiscDP2SourceFixed | B11 , SDIV = MiscDP2SourceFixed | B11 | B10 , LSLV = MiscDP2SourceFixed | B13 , LSRV = MiscDP2SourceFixed | B13 | B10 , ASRV = MiscDP2SourceFixed | B13 | B11 } |
enum | MiscDP3SourceOp { MiscDP3SourceMask = 0x1f000000 , MiscDP3SourceFixed = DPRegisterFixed | B28 | B24 , MADDW = MiscDP3SourceFixed , MADD = MiscDP3SourceFixed | B31 , MSUBW = MiscDP3SourceFixed | B15 , MSUB = MiscDP3SourceFixed | B31 | B15 , SMULH = MiscDP3SourceFixed | B31 | B22 , UMULH = MiscDP3SourceFixed | B31 | B23 | B22 , SMADDL = MiscDP3SourceFixed | B31 | B21 , UMADDL = MiscDP3SourceFixed | B31 | B23 | B21 , SMSUBL = MiscDP3SourceFixed | B31 | B21 | B15 , UMSUBL = MiscDP3SourceFixed | B31 | B23 | B21 | B15 } |
enum | LogicalShiftOp { LogicalShiftMask = 0x1f000000 , LogicalShiftFixed = DPRegisterFixed , AND = 0 , BIC = 14 , ORR = 12 , ORN = LogicalShiftFixed | B29 | B21 , EOR = 1 , EON = LogicalShiftFixed | B30 | B21 , ANDS = LogicalShiftFixed | B30 | B29 , BICS = LogicalShiftFixed | B30 | B29 | B21 } |
enum | SIMDCopyOp { SIMDCopyMask = 0x9fe08400 , SIMDCopyFixed = DPSimd1Fixed | B10 , VDUPI = SIMDCopyFixed | B30 | B11 , VINSI = SIMDCopyFixed | B30 | B12 | B11 , VMOVW = SIMDCopyFixed | B13 | B12 | B11 , VMOVX = SIMDCopyFixed | B30 | B13 | B12 | B11 , VDUP = SIMDCopyFixed | B30 , VINS = SIMDCopyFixed | B30 | B29 } |
enum | SIMDThreeSameOp { SIMDThreeSameMask = 0x9f200400 , SIMDThreeSameFixed = DPSimd1Fixed | B21 | B10 , VAND = SIMDThreeSameFixed | B30 | B12 | B11 , VORR = SIMDThreeSameFixed | B30 | B23 | B12 | B11 , VEOR = SIMDThreeSameFixed | B30 | B29 | B12 | B11 , VADDW = SIMDThreeSameFixed | B30 | B23 | B15 , VADDX = SIMDThreeSameFixed | B30 | B23 | B22 | B15 , VSUBW = SIMDThreeSameFixed | B30 | B29 | B23 | B15 , VSUBX = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 , VADDS = SIMDThreeSameFixed | B30 | B15 | B14 | B12 , VADDD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B12 , VSUBS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B12 , VSUBD = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B12 , VMULS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B12 | B11 , VMULD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B12 | B11 , VDIVS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 | B12 | B11 , VDIVD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 | B12 | B11 , VCEQS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 , VCEQD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 , VCGES = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 , VCGED = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 , VCGTS = SIMDThreeSameFixed | B30 | B29 | B23 | B15 | B14 | B13 , VCGTD = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 , VMAXS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 , VMAXD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 | B12 , VMINS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 , VMIND = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , VRECPSS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 | B11 , VRSQRTSS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 | B11 } |
enum | SIMDTwoRegOp { SIMDTwoRegMask = 0x9f3e0c00 , SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11 , VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12 , VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12 , VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12 , VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12 , VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12 , VSQRTS = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B13 | B12 , VSQRTD , VRECPES = SIMDTwoRegFixed | B30 | B23 | B16 | B15 | B14 | B12 , VRSQRTES = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B12 } |
enum | FPCompareOp { FPCompareMask = 0xffa0fc07 , FPCompareFixed = FPFixed | B21 | B13 , FCMPD = FPCompareFixed | B22 , FCMPZD = FPCompareFixed | B22 | B3 } |
enum | FPOneSourceOp { FPOneSourceMask = 0x5f207c00 , FPOneSourceFixed = FPFixed | B21 | B14 , FMOVDD = FPOneSourceFixed | B22 , FABSD = FPOneSourceFixed | B22 | B15 , FNEGD = FPOneSourceFixed | B22 | B16 , FSQRTD = FPOneSourceFixed | B22 | B16 | B15 , FCVTDS = FPOneSourceFixed | B15 | B17 , FCVTSD = FPOneSourceFixed | B22 | B17 } |
enum | FPTwoSourceOp { FPTwoSourceMask = 0xff200c00 , FPTwoSourceFixed = FPFixed | B21 | B11 , FMULD = FPTwoSourceFixed | B22 , FDIVD = FPTwoSourceFixed | B22 | B12 , FADDD = FPTwoSourceFixed | B22 | B13 , FSUBD = FPTwoSourceFixed | B22 | B13 | B12 } |
enum | FPImmOp { FPImmMask = 0x5f201c00 , FPImmFixed = FPFixed | B21 | B12 , FMOVSI = FPImmFixed , FMOVDI = FPImmFixed | B22 } |
enum | FPIntCvtOp { FPIntCvtMask = 0x5f00fc00 , FPIntCvtFixed = FPFixed | B21 , FMOVRS = FPIntCvtFixed | B18 | B17 , FMOVSR = FPIntCvtFixed | B18 | B17 | B16 , FMOVRD = FPIntCvtFixed | B22 | B18 | B17 , FMOVDR = FPIntCvtFixed | B22 | B18 | B17 | B16 , FCVTZS_D = FPIntCvtFixed | B22 | B20 | B19 , FCVTMS_D = FPIntCvtFixed | B22 | B20 , FCVTPS_D = FPIntCvtFixed | B22 | B19 , SCVTFD = FPIntCvtFixed | B22 | B17 } |
enum | Shift { kNoShift = -1 , LSL = 0 , LSR = 1 , ASR = 2 , ROR = 3 , kMaxShift = 4 , kNoShift = -1 , LSL = 0 , LSR = 1 , ASR = 2 , ROR = 3 , kMaxShift = 4 } |
enum | Extend { kNoExtend = -1 , UXTB = 0 , UXTH = 1 , UXTW = 2 , UXTX = 3 , SXTB = 4 , SXTH = 5 , SXTW = 6 , SXTX = 7 , kMaxExtend = 8 } |
enum | R31Type { R31IsSP , R31IsZR } |
enum | InstructionFields { kConditionShift = 28 , kConditionBits = 4 , kTypeShift = 25 , kTypeBits = 3 , kLinkShift = 24 , kLinkBits = 1 , kUShift = 23 , kUBits = 1 , kOpcodeShift = 21 , kOpcodeBits = 4 , kSShift = 20 , kSBits = 1 , kRnShift = 16 , kRnBits = 4 , kRdShift = 12 , kRdBits = 4 , kRsShift = 8 , kRsBits = 4 , kRmShift = 0 , kRmBits = 4 , kRotateShift = 8 , kRotateBits = 4 , kImmed8Shift = 0 , kImmed8Bits = 8 , kShiftImmShift = 7 , kShiftRegisterShift = 8 , kShiftImmBits = 5 , kShiftShift = 5 , kShiftBits = 2 , kOffset12Shift = 0 , kOffset12Bits = 12 , kOffset12Mask = 0x00000fff , kMulRdShift = 16 , kMulRdBits = 4 , kMulRnShift = 12 , kMulRnBits = 4 , kLdrExRnShift = 16 , kLdrExRtShift = 12 , kStrExRnShift = 16 , kStrExRdShift = 12 , kStrExRtShift = 0 , kMediaOp1Shift = 20 , kMediaOp1Bits = 5 , kMediaOp2Shift = 5 , kMediaOp2Bits = 3 , kDivRdShift = 16 , kDivRdBits = 4 , kDivRmShift = 8 , kDivRmBits = 4 , kDivRnShift = 0 , kDivRnBits = 4 , kBitFieldExtractWidthShift = 16 , kBitFieldExtractWidthBits = 5 , kBitFieldExtractLSBShift = 7 , kBitFieldExtractLSBBits = 5 , kBitFieldExtractRnShift = 0 , kBitFieldExtractRnBits = 4 , kCRmShift = 0 , kCRmBits = 4 , kOpc2Shift = 5 , kOpc2Bits = 3 , kCoprocShift = 8 , kCoprocBits = 4 , kCRnShift = 16 , kCRnBits = 4 , kOpc1Shift = 21 , kOpc1Bits = 3 , kBranchOffsetMask = 0x00ffffff , kSShift = 20 , kSBits = 1 , kSFShift = 31 , kSFBits = 1 , kSzShift = 30 , kSzBits = 2 , kRdShift = 12 , kRdBits = 4 , kRnShift = 16 , kRnBits = 4 , kRaShift = 10 , kRaBits = 5 , kRmShift = 0 , kRmBits = 4 , kRtShift = 0 , kRtBits = 5 , kRt2Shift = 10 , kRt2Bits = 5 , kRsShift = 8 , kRsBits = 4 , kVdShift = 0 , kVdBits = 5 , kVnShift = 5 , kVnBits = 5 , kVmShift = 16 , kVmBits = 5 , kVtShift = 0 , kVtBits = 5 , kVt2Shift = 10 , kVt2Bits = 5 , kImm3Shift = 10 , kImm3Bits = 3 , kImm4Shift = 11 , kImm4Bits = 4 , kImm5Shift = 16 , kImm5Bits = 5 , kImm6Shift = 10 , kImm6Bits = 6 , kImm7Shift = 15 , kImm7Bits = 7 , kImm7Mask = 0x7f << kImm7Shift , kImm8Shift = 13 , kImm8Bits = 8 , kImm9Shift = 12 , kImm9Bits = 9 , kImm12Shift = 10 , kImm12Bits = 12 , kImm12Mask = 0xfff << kImm12Shift , kImm12ShiftShift = 22 , kImm12ShiftBits = 2 , kImm14Shift = 5 , kImm14Bits = 14 , kImm14Mask = 0x3fff << kImm14Shift , kImm16Shift = 5 , kImm16Bits = 16 , kImm16Mask = 0xffff << kImm16Shift , kImm19Shift = 5 , kImm19Bits = 19 , kImm19Mask = 0x7ffff << kImm19Shift , kImm26Shift = 0 , kImm26Bits = 26 , kImm26Mask = 0x03ffffff << kImm26Shift , kCondShift = 0 , kCondBits = 4 , kCondMask = 0xf << kCondShift , kSelCondShift = 12 , kSelCondBits = 4 , kNShift = 22 , kNBits = 1 , kImmRShift = 16 , kImmRBits = 6 , kImmSShift = 10 , kImmSBits = 6 , kHWShift = 21 , kHWBits = 2 , kAddShiftExtendShift = 21 , kAddShiftExtendBits = 1 , kShiftTypeShift = 22 , kShiftTypeBits = 2 , kExtendTypeShift = 13 , kExtendTypeBits = 3 , kHintCRmShift = 8 , kHintCRmBits = 4 , kHintOp2Shift = 5 , kHintOp2Bits = 3 } |
enum | ScaleFactor { TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
enum | AlignmentStrategy { kAlignedToValueSize , kAlignedToValueSizeBut8AlignedTo4 , kAlignedToWordSize , kAlignedToWordSizeAndValueSize } |
enum | ExtensionStrategy { kNotExtended , kExtendedTo4 , kExtendedTo8 } |
enum | Register { R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , FP = R11 , NOTFP = R7 , IP = R12 , SP = R13 , LR = R14 , PC = R15 , R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , R16 = 16 , R17 = 17 , R18 = 18 , R19 = 19 , R20 = 20 , R21 = 21 , R22 = 22 , R23 = 23 , R24 = 24 , R25 = 25 , R26 = 26 , R27 = 27 , R28 = 28 , R29 = 29 , R30 = 30 , R31 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , kNoRegister2 = -2 , CSP = 32 , ZR = 33 , IP0 = R16 , IP1 = R17 , SP = R13 , FP = R11 , LR = R14 , EAX = 0 , ECX = 1 , EDX = 2 , EBX = 3 , ESP = 4 , EBP = 5 , ESI = 6 , EDI = 7 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , ZR = 33 , RA = 1 , SP = R13 , GP = 3 , TP = 4 , T0 = 5 , T1 = 6 , T2 = 7 , FP = R11 , S1 = 1 , A0 = 10 , A1 = 11 , A2 = 12 , A3 = 13 , A4 = 14 , A5 = 15 , A6 = 16 , A7 = 17 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , T3 = 28 , T4 = 29 , T5 = 30 , T6 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , RA2 = T0 , S0 = 0 , RAX = 0 , RCX = 1 , RDX = 2 , RBX = 3 , RSP = 4 , RBP = 5 , RSI = 6 , RDI = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 } |
enum | ByteRegister { AL = 14 , CL = 1 , DL = 2 , BL = UnconditionalBranchFixed | B31 , AH = 4 , CH = 5 , DH = 6 , BH = 7 , kNumberOfByteRegisters = 8 , kNoByteRegister = -1 , AL = 14 , CL = 1 , DL = 2 , BL = UnconditionalBranchFixed | B31 , AH = 4 , CH = 5 , DH = 6 , BH = 7 , SPL = 4 | 0x10 , BPL = 5 | 0x10 , SIL = 6 | 0x10 , DIL = 7 | 0x10 , R8B = 8 , R9B = 9 , R10B = 10 , R11B = 11 , R12B = 12 , R13B = 13 , R14B = 14 , R15B = 15 , kNumberOfByteRegisters = 8 , kNoByteRegister = -1 } |
enum | XmmRegister { XMM0 = 0 , XMM1 = 1 , XMM2 = 2 , XMM3 = 3 , XMM4 = 4 , XMM5 = 5 , XMM6 = 6 , XMM7 = 7 , kNumberOfXmmRegisters = 8 , kNoXmmRegister = -1 , XMM0 = 0 , XMM1 = 1 , XMM2 = 2 , XMM3 = 3 , XMM4 = 4 , XMM5 = 5 , XMM6 = 6 , XMM7 = 7 , XMM8 = 8 , XMM9 = 9 , XMM10 = 10 , XMM11 = 11 , XMM12 = 12 , XMM13 = 13 , XMM14 = 14 , XMM15 = 15 , kNumberOfXmmRegisters = 8 , kNoXmmRegister = -1 } |
enum | ScaleFactor { TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
enum | Register { R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , FP = R11 , NOTFP = R7 , IP = R12 , SP = R13 , LR = R14 , PC = R15 , R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , R16 = 16 , R17 = 17 , R18 = 18 , R19 = 19 , R20 = 20 , R21 = 21 , R22 = 22 , R23 = 23 , R24 = 24 , R25 = 25 , R26 = 26 , R27 = 27 , R28 = 28 , R29 = 29 , R30 = 30 , R31 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , kNoRegister2 = -2 , CSP = 32 , ZR = 33 , IP0 = R16 , IP1 = R17 , SP = R13 , FP = R11 , LR = R14 , EAX = 0 , ECX = 1 , EDX = 2 , EBX = 3 , ESP = 4 , EBP = 5 , ESI = 6 , EDI = 7 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , ZR = 33 , RA = 1 , SP = R13 , GP = 3 , TP = 4 , T0 = 5 , T1 = 6 , T2 = 7 , FP = R11 , S1 = 1 , A0 = 10 , A1 = 11 , A2 = 12 , A3 = 13 , A4 = 14 , A5 = 15 , A6 = 16 , A7 = 17 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , T3 = 28 , T4 = 29 , T5 = 30 , T6 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , RA2 = T0 , S0 = 0 , RAX = 0 , RCX = 1 , RDX = 2 , RBX = 3 , RSP = 4 , RBP = 5 , RSI = 6 , RDI = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 } |
enum | FRegister { FT0 = 0 , FT1 = 1 , FT2 = 2 , FT3 = 3 , FT4 = 4 , FT5 = 5 , FT6 = 6 , FT7 = 7 , FS0 = 8 , FS1 = 9 , FA0 = 10 , FA1 = 11 , FA2 = 12 , FA3 = 13 , FA4 = 14 , FA5 = 15 , FA6 = 16 , FA7 = 17 , FS2 = 18 , FS3 = 19 , FS4 = 20 , FS5 = 21 , FS6 = 22 , FS7 = 23 , FS8 = 24 , FS9 = 25 , FS10 = 26 , FS11 = 27 , FT8 = 28 , FT9 = 29 , FT10 = 30 , FT11 = 31 } |
enum | Condition { kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , kSpecialCondition = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , OVERFLOW = VS , NO_OVERFLOW = VC , BELOW = 2 , ABOVE_EQUAL = 3 , EQUAL = EQ , NOT_EQUAL = NE , BELOW_EQUAL = 6 , ABOVE = 7 , SIGN = 8 , NOT_SIGN = 9 , PARITY_EVEN = 10 , PARITY_ODD = 11 , LESS = LT , GREATER_EQUAL = GE , LESS_EQUAL = LE , GREATER = GT , ZERO = EQUAL , NOT_ZERO = NOT_EQUAL , NEGATIVE = SIGN , POSITIVE = NOT_SIGN , CARRY = BELOW , NOT_CARRY = ABOVE_EQUAL , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , kInvalidCondition = 16 } |
enum | ScaleFactor { TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
enum | Opcode { kNoOperand = -1 , AND = 0 , EOR = 1 , SUB = 2 , RSB = 3 , ADD = 4 , ADC = 5 , SBC = 6 , RSC = 7 , TST = 8 , TEQ = 9 , CMP = 10 , CMN = 11 , ORR = 12 , MOV = 13 , BIC = 14 , MVN = 15 , kMaxOperand = 16 , LUI = 0b0110111 , AUIPC = 0b0010111 , JAL = 0b1101111 , JALR = 0b1100111 , BRANCH = 0b1100011 , LOAD = 0b0000011 , STORE = 0b0100011 , OPIMM = 0b0010011 , OP = 0b0110011 , MISCMEM = 0b0001111 , SYSTEM = 0b1110011 , OP32 = 0b0111011 , OPIMM32 = 0b0011011 , AMO = 0b0101111 , LOADFP = 0b0000111 , STOREFP = 0b0100111 , FMADD = 0b1000011 , FMSUB = 0b1000111 , FNMSUB = 0b1001011 , FNMADD = 0b1001111 , OPFP = 0b1010011 } |
enum | Funct12 { ECALL = 0 , EBREAK = 1 } |
enum | Funct3 { F3_0 = 0 , F3_1 = 1 , BEQ = 0b000 , BNE = 0b001 , BLT = 0b100 , BGE = 0b101 , BLTU = 0b110 , BGEU = 0b111 , LB = 0b000 , LH = 0b001 , LW = 0b010 , LBU = 0b100 , LHU = 0b101 , LWU = 0b110 , LD = 0b011 , SB = 0b000 , SH = 0b001 , SW = 0b010 , SD = 0b011 , ADDI = AddSubImmFixed , SLLI = 0b001 , SLTI = 0b010 , SLTIU = 0b011 , XORI = 0b100 , SRI = 0b101 , ORI = 0b110 , ANDI = LogicalImmFixed , ADD = 4 , SLL = 0b001 , SLT = 0b010 , SLTU = 0b011 , XOR = 0b100 , SR = 0b101 , OR = 0b110 , AND = 0 , FENCE = 0b000 , FENCEI = 0b001 , CSRRW = 0b001 , CSRRS = 0b010 , CSRRC = 0b011 , CSRRWI = 0b101 , CSRRSI = 0b110 , CSRRCI = 0b111 , MUL = 0b000 , MULH = 0b001 , MULHSU = 0b010 , MULHU = 0b011 , DIV = 0b100 , DIVU = 0b101 , REM = 0b110 , REMU = 0b111 , MULW = 0b000 , DIVW = 0b100 , DIVUW = 0b101 , REMW = 0b110 , REMUW = 0b111 , WIDTH8 = 0b000 , WIDTH16 = 0b001 , WIDTH32 = 0b010 , WIDTH64 = 0b011 , S = 0b010 , D = 0b011 , J = 0b000 , JN = 0b001 , JX = 0b010 , FMIN = 0b000 , FMAX = 0b001 , FEQ = 0b010 , FLT = 0b001 , FLE = 0b000 , SH1ADD = 0b010 , SH2ADD = 0b100 , SH3ADD = 0b110 , F3_COUNT = 0b001 , MAX = 0b110 , MAXU = 0b111 , MIN = 0b100 , MINU = 0b101 , CLMUL = 0b001 , CLMULH = 0b011 , CLMULR = 0b010 , SEXT = 0b001 , ZEXT = 0b100 , ROL = 0b001 , ROR = 3 , BCLR = 0b001 , BEXT = 0b101 , F3_BINV = 0b001 , F3_BSET = 0b001 } |
enum | Funct7 { F7_0 = 0 , SRA = 0b0100000 , SUB = 2 , MULDIV = 0b0000001 , FADDS = 0b0000000 , FSUBS = 0b0000100 , FMULS = 0b0001000 , FDIVS = 0b0001100 , FSQRTS = 0b0101100 , FSGNJS = 0b0010000 , FMINMAXS = 0b0010100 , FCMPS = 0b1010000 , FCLASSS = 0b1110000 , FCVTintS = 0b1100000 , FCVTSint = 0b1101000 , FMVXW = 0b1110000 , FMVWX = 0b1111000 , FADDD = FPTwoSourceFixed | B22 | B13 , FSUBD = FPTwoSourceFixed | B22 | B13 | B12 , FMULD = FPTwoSourceFixed | B22 , FDIVD = FPTwoSourceFixed | B22 | B12 , FSQRTD = FPOneSourceFixed | B22 | B16 | B15 , FSGNJD = 0b0010001 , FMINMAXD = 0b0010101 , FCVTS = 0b0100000 , FCVTD = 0b0100001 , FCMPD = FPCompareFixed | B22 , FCLASSD = 0b1110001 , FCVTintD = 0b1100001 , FCVTDint = 0b1101001 , FMVXD = 0b1110001 , FMVDX = 0b1111001 , ADDUW = 0b0000100 , SHADD = 0b0010000 , SLLIUW = 0b0000100 , COUNT = 0b0110000 , MINMAXCLMUL = 0b0000101 , ROTATE = 0b0110000 , BCLRBEXT = 0b0100100 , BINV = 0b0110100 , BSET = 0b0010100 } |
enum | Funct5 { LR = R14 , SC = 0b00011 , AMOSWAP = 0b00001 , AMOADD = 0b00000 , AMOXOR = 0b00100 , AMOAND = 0b01100 , AMOOR = 0b01000 , AMOMIN = 0b10000 , AMOMAX = 0b10100 , AMOMINU = 0b11000 , AMOMAXU = 0b11100 , LOADORDERED = 0b00110 , STOREORDERED = 0b00111 } |
enum | Funct2 { F2_S = 0b00 , F2_D = 0b01 } |
enum | RoundingMode { RNE = 0b000 , RTZ = 0b001 , RDN = 0b010 , RUP = 0b011 , RMM = 0b100 , DYN = 0b111 } |
enum | FcvtRs2 { W = 0b00000 , WU = 0b00001 , L = 0b00010 , LU = 0b00011 } |
enum | FClass { kFClassNegInfinity = 1 << 0 , kFClassNegNormal = 1 << 1 , kFClassNegSubnormal = 1 << 2 , kFClassNegZero = 1 << 3 , kFClassPosZero = 1 << 4 , kFClassPosSubnormal = 1 << 5 , kFClassPosNormal = 1 << 6 , kFClassPosInfinity = 1 << 7 , kFClassSignallingNan = 1 << 8 , kFClassQuietNan = 1 << 9 } |
enum | HartEffects { kWrite = 1 << 0 , kRead = 1 << 1 , kOutput = 1 << 2 , kInput = 1 << 3 , kMemory = kWrite | kRead , kIO = kOutput | kInput , kAll = kMemory | kIO } |
enum | COpcode { C_OP_MASK = 0b1110000000000011 , C_ADDI4SPN = 0b0000000000000000 , C_FLD = 0b0010000000000000 , C_LW = 0b0100000000000000 , C_FLW = 0b0110000000000000 , C_LD = 0b0110000000000000 , C_FSD = 0b1010000000000000 , C_SW = 0b1100000000000000 , C_FSW = 0b1110000000000000 , C_SD = 0b1110000000000000 , C_ADDI = 0b0000000000000001 , C_JAL = 0b0010000000000001 , C_ADDIW = 0b0010000000000001 , C_LI = 0b0100000000000001 , C_ADDI16SP = 0b0110000000000001 , C_LUI = 0b0110000000000001 , C_MISCALU = 0b1000000000000001 , C_MISCALU_MASK = 0b1110110000000011 , C_SRLI = 0b1000000000000001 , C_SRAI = 0b1000010000000001 , C_ANDI = 0b1000100000000001 , C_RR = 0b1000110000000001 , C_RR_MASK = 0b1111110001100011 , C_SUB = 0b1000110000000001 , C_XOR = 0b1000110000100001 , C_OR = 0b1000110001000001 , C_AND = 0b1000110001100001 , C_SUBW = 0b1001110000000001 , C_ADDW = 0b1001110000100001 , C_J = 0b1010000000000001 , C_BEQZ = 0b1100000000000001 , C_BNEZ = 0b1110000000000001 , C_SLLI = 0b0000000000000010 , C_FLDSP = 0b0010000000000010 , C_LWSP = 0b0100000000000010 , C_FLWSP = 0b0110000000000010 , C_LDSP = 0b0110000000000010 , C_JR = 0b1000000000000010 , C_MV = 0b1000000000000010 , C_JALR = 0b1001000000000010 , C_ADD = 0b1001000000000010 , C_FSDSP = 0b1010000000000010 , C_SWSP = 0b1100000000000010 , C_FSWSP = 0b1110000000000010 , C_SDSP = 0b1110000000000010 , C_NOP = 0b0000000000000001 , C_EBREAK = 0b1001000000000010 } |
enum | Register { R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , FP = R11 , NOTFP = R7 , IP = R12 , SP = R13 , LR = R14 , PC = R15 , R0 = 0 , R1 = 1 , R2 = 2 , R3 = 3 , R4 = 4 , R5 = 5 , R6 = 6 , R7 = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , R16 = 16 , R17 = 17 , R18 = 18 , R19 = 19 , R20 = 20 , R21 = 21 , R22 = 22 , R23 = 23 , R24 = 24 , R25 = 25 , R26 = 26 , R27 = 27 , R28 = 28 , R29 = 29 , R30 = 30 , R31 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , kNoRegister2 = -2 , CSP = 32 , ZR = 33 , IP0 = R16 , IP1 = R17 , SP = R13 , FP = R11 , LR = R14 , EAX = 0 , ECX = 1 , EDX = 2 , EBX = 3 , ESP = 4 , EBP = 5 , ESI = 6 , EDI = 7 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , ZR = 33 , RA = 1 , SP = R13 , GP = 3 , TP = 4 , T0 = 5 , T1 = 6 , T2 = 7 , FP = R11 , S1 = 1 , A0 = 10 , A1 = 11 , A2 = 12 , A3 = 13 , A4 = 14 , A5 = 15 , A6 = 16 , A7 = 17 , S2 = 2 , S3 = 3 , S4 = 4 , S5 = 5 , S6 = 6 , S7 = 7 , S8 = 8 , S9 = 9 , S10 = 10 , S11 = 11 , T3 = 28 , T4 = 29 , T5 = 30 , T6 = 31 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 , RA2 = T0 , S0 = 0 , RAX = 0 , RCX = 1 , RDX = 2 , RBX = 3 , RSP = 4 , RBP = 5 , RSI = 6 , RDI = 7 , R8 = 8 , R9 = 9 , R10 = 10 , R11 = 11 , R12 = 12 , R13 = 13 , R14 = 14 , R15 = 15 , kNumberOfCpuRegisters = 16 , kNoRegister = -1 } |
enum | ByteRegister { AL = 14 , CL = 1 , DL = 2 , BL = UnconditionalBranchFixed | B31 , AH = 4 , CH = 5 , DH = 6 , BH = 7 , kNumberOfByteRegisters = 8 , kNoByteRegister = -1 , AL = 14 , CL = 1 , DL = 2 , BL = UnconditionalBranchFixed | B31 , AH = 4 , CH = 5 , DH = 6 , BH = 7 , SPL = 4 | 0x10 , BPL = 5 | 0x10 , SIL = 6 | 0x10 , DIL = 7 | 0x10 , R8B = 8 , R9B = 9 , R10B = 10 , R11B = 11 , R12B = 12 , R13B = 13 , R14B = 14 , R15B = 15 , kNumberOfByteRegisters = 8 , kNoByteRegister = -1 } |
enum | XmmRegister { XMM0 = 0 , XMM1 = 1 , XMM2 = 2 , XMM3 = 3 , XMM4 = 4 , XMM5 = 5 , XMM6 = 6 , XMM7 = 7 , kNumberOfXmmRegisters = 8 , kNoXmmRegister = -1 , XMM0 = 0 , XMM1 = 1 , XMM2 = 2 , XMM3 = 3 , XMM4 = 4 , XMM5 = 5 , XMM6 = 6 , XMM7 = 7 , XMM8 = 8 , XMM9 = 9 , XMM10 = 10 , XMM11 = 11 , XMM12 = 12 , XMM13 = 13 , XMM14 = 14 , XMM15 = 15 , kNumberOfXmmRegisters = 8 , kNoXmmRegister = -1 } |
enum | RexBits { REX_NONE = 0 , REX_B = 1 << 0 , REX_X = 1 << 1 , REX_R = 1 << 2 , REX_W = 1 << 3 , REX_PREFIX = 1 << 6 } |
enum | ScaleFactor { TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 , TIMES_1 = 0 , TIMES_2 = 1 , TIMES_4 = 2 , TIMES_8 = 3 , TIMES_16 = 4 , TIMES_COMPRESSED_WORD_SIZE = TIMES_WORD_SIZE , TIMES_COMPRESSED_HALF_WORD_SIZE = TIMES_COMPRESSED_WORD_SIZE - 1 } |
enum | Condition { kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , kSpecialCondition = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , kNoCondition = -1 , EQ = 0 , NE = 1 , CS = 2 , CC = 3 , MI = 4 , PL = 5 , VS = 6 , VC = 7 , HI = 8 , LS = 9 , GE = 10 , LT = 11 , GT = 12 , LE = 13 , AL = 14 , NV = 15 , kNumberOfConditions = 16 , EQUAL = EQ , ZERO = EQUAL , NOT_EQUAL = NE , NOT_ZERO = NOT_EQUAL , LESS = LT , LESS_EQUAL = LE , GREATER_EQUAL = GE , GREATER = GT , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , OVERFLOW = VS , NO_OVERFLOW = VC , kInvalidCondition = 16 , OVERFLOW = VS , NO_OVERFLOW = VC , BELOW = 2 , ABOVE_EQUAL = 3 , EQUAL = EQ , NOT_EQUAL = NE , BELOW_EQUAL = 6 , ABOVE = 7 , SIGN = 8 , NOT_SIGN = 9 , PARITY_EVEN = 10 , PARITY_ODD = 11 , LESS = LT , GREATER_EQUAL = GE , LESS_EQUAL = LE , GREATER = GT , ZERO = EQUAL , NOT_ZERO = NOT_EQUAL , NEGATIVE = SIGN , POSITIVE = NOT_SIGN , CARRY = BELOW , NOT_CARRY = ABOVE_EQUAL , UNSIGNED_LESS = CC , UNSIGNED_LESS_EQUAL = LS , UNSIGNED_GREATER = HI , UNSIGNED_GREATER_EQUAL = CS , kInvalidCondition = 16 } |
enum | CpuInfoIndices { kCpuInfoProcessor = 0 , kCpuInfoModel = 1 , kCpuInfoHardware = 2 , kCpuInfoFeatures = 3 , kCpuInfoArchitecture = 4 , kCpuInfoMax = 5 } |
enum | CpuInfoMethod { kCpuInfoCpuId , kCpuInfoSystem , kCpuInfoNone , kCpuInfoDefault } |
enum | Dart_ExceptionPauseInfo { kNoPauseOnExceptions = 1 , kPauseOnUnhandledExceptions , kPauseOnAllExceptions , kInvalidExceptionPauseInfo } |
enum | Dart_IsolateEvent { kCreated = 0 , kInterrupted , kShutdown } |
enum class | ExperimentalFeature { inference_update_3 , inline_class , inference_update_2 , sealed_class , class_modifiers , records , patterns , unnamed_libraries , inference_update_1 , enhanced_enums , named_arguments_anywhere , super_parameters , constructor_tearoffs , generic_metadata , triple_shift , nonfunction_type_aliases , non_nullable , extension_methods , constant_update_2018 , control_flow_collections , set_literals , spread_collections } |
enum | Generation { kNew , kOld , kImm } |
enum | RootSlices { kIsolate = 0 , kObjectIdRing = 1 , kNumFixedRootSlices = 2 , kIsolate = 0 , kObjectIdRing = 1 , kNumRootSlices } |
enum | WeakSlices { kWeakHandles = 0 , kWeakTables , kRememberedSet , kNumWeakSlices , kWeakHandles = 0 , kWeakTables , kProgressBars , kRememberLiveTemporaries , kPruneWeak , kNumWeakSlices } |
enum | { kForwardingMask = 1 << UntaggedObject::kCardRememberedBit , kNotForwarded = 0 , kForwarded = kForwardingMask } |
enum | RootSlices { kIsolate = 0 , kObjectIdRing = 1 , kNumFixedRootSlices = 2 , kIsolate = 0 , kObjectIdRing = 1 , kNumRootSlices } |
enum | WeakSlices { kWeakHandles = 0 , kWeakTables , kRememberedSet , kNumWeakSlices , kWeakHandles = 0 , kWeakTables , kProgressBars , kRememberLiveTemporaries , kPruneWeak , kNumWeakSlices } |
enum class | GCType { kScavenge , kEvacuate , kStartConcurrentMark , kMarkSweep , kMarkCompact } |
enum class | GCReason { kNewSpace , kStoreBuffer , kPromotion , kOldSpace , kFinalize , kFull , kExternal , kIdle , kDestroyed , kDebugging , kCatchUp } |
enum | MarkExpectation { kForbidMarked , kAllowMarked , kRequireMarked } |
enum | JSONRpcErrorCode { kParseError = -32700 , kInvalidRequest = -32600 , kMethodNotFound = -32601 , kInvalidParams = -32602 , kInternalError = -32603 , kExtensionError = -32000 , kFeatureDisabled = 100 , kCannotAddBreakpoint = 102 , kStreamAlreadySubscribed = 103 , kStreamNotSubscribed = 104 , kIsolateMustBeRunnable = 105 , kIsolateMustBePaused = 106 , kCannotResume = 107 , kIsolateIsReloading = 108 , kIsolateReloadBarred = 109 , kIsolateMustHaveReloaded = 110 , kServiceAlreadyRegistered = 111 , kServiceDisappeared = 112 , kExpressionCompilationError = 113 , kInvalidTimelineRequest = 114 , kFileSystemAlreadyExists = 1001 , kFileSystemDoesNotExist = 1002 , kFileDoesNotExist = 1003 } |
enum class | MessagePhase { kBeforeTypes = 0 , kTypes = 1 , kCanonicalInstances = 2 , kNonCanonicalInstances = 3 , kNumPhases = 4 } |
enum | TypedDataViewFormat { kTypedDataViewFromC , kTypedDataViewFromDart } |
enum | QualifiedFunctionLibKind { kQualifiedFunctionLibKindLibUrl , kQualifiedFunctionLibKindLibName } |
enum class | Nullability : uint8_t { kNullable = 0 , |