90 : flow_graph_(flow_graph),
91 reaching_defs_(flow_graph),
92 value_representations_(flow_graph.max_vreg()),
94 postorder_(flow_graph.postorder()),
95 instructions_(),
96 block_entries_(),
97 extra_loop_info_(),
98 liveness_(flow_graph),
99 vreg_count_(flow_graph.max_vreg()),
100 live_ranges_(flow_graph.max_vreg()),
101 unallocated_cpu_(),
102 unallocated_fpu_(),
103 cpu_regs_(),
104 fpu_regs_(),
105 blocked_cpu_registers_(),
106 blocked_fpu_registers_(),
107 spilled_(),
108 safepoints_(),
109 register_kind_(),
110 number_of_registers_(0),
111 registers_(),
112 blocked_registers_(),
113 unallocated_(),
114 spill_slots_(),
115 quad_spill_slots_(),
116 untagged_spill_slots_(),
117 cpu_spill_slot_count_(0),
118 intrinsic_mode_(intrinsic_mode) {
119 for (intptr_t i = 0; i < vreg_count_; i++) {
120 live_ranges_.Add(nullptr);
121 }
122 for (intptr_t i = 0; i < vreg_count_; i++) {
123 value_representations_.
Add(kNoRepresentation);
124 }
125
126
127
130 blocked_cpu_registers_[i] = true;
131 }
132 }
133
134
135 blocked_fpu_registers_[
FpuTMP] =
true;
136
137
138
139
140 if (intrinsic_mode) {
142
143#if !defined(TARGET_ARCH_IA32)
144
145
146 blocked_cpu_registers_[
CODE_REG] =
true;
147#endif
148 }
149}
static const GrowableArray< BlockEntryInstr * > & BlockOrderForAllocation(const FlowGraph &flow_graph)
const Register ARGS_DESC_REG
constexpr RegList kDartAvailableCpuRegs