5#ifndef RUNTIME_VM_PORT_SET_H_
6#define RUNTIME_VM_PORT_SET_H_
33 dirty_counter_ = ports_->dirty_counter_;
38 ASSERT(index_ >= 0 && index_ < ports_->capacity_);
40 return ports_->map_[index_];
43 ASSERT(index_ >= 0 && index_ < ports_->capacity_);
45 return ports_->map_[index_];
50 return ports_ == other.ports_ && index_ == other.index_;
55 return !(*
this == other);
61 while (index_ < ports_->capacity_) {
77 ports_->map_[index_] =
T();
89 bool WasModified()
const {
90 return dirty_counter_ != ports_->dirty_counter_;
97 intptr_t dirty_counter_ = 0;
102 const intptr_t kInitialCapacity = 8;
104 map_ =
new T[kInitialCapacity];
105 capacity_ = kInitialCapacity;
115 for (intptr_t
i = 0;
i < capacity_; ++
i) {
116 auto& entry = map_[
i];
129 ASSERT(FindIndexOfPort(entry.port) < 0);
130 intptr_t index = entry.port % capacity_;
135 index = (index + 1) % capacity_;
145 ASSERT(FindIndexOfPort(entry.port) >= 0);
149 MaintainInvariants();
157 const intptr_t index = FindIndexOfPort(
port);
158 if (index >= 0)
return Iterator(
this, index);
177 intptr_t index =
port % capacity_;
178 intptr_t start_index = index;
179 T entry = map_[index];
181 if (entry.port ==
port) {
184 index = (index + 1) % capacity_;
186 ASSERT(index != start_index);
192 void MaintainInvariants() {
193 const intptr_t
empty = capacity_ - used_ - deleted_;
194 if (used_ > ((capacity_ / 4) * 3)) {
196 Rehash(capacity_ * 2);
197 }
else if (
empty < deleted_) {
204 void Rehash(intptr_t new_capacity) {
205 T* new_ports =
new T[new_capacity];
207 for (
auto entry : *
this) {
208 intptr_t new_index = entry.port % new_capacity;
209 while (new_ports[new_index].
port != 0) {
210 new_index = (new_index + 1) % new_capacity;
212 new_ports[new_index] = entry;
216 capacity_ = new_capacity;
225 intptr_t capacity_ = 0;
227 intptr_t deleted_ = 0;
230 intptr_t dirty_counter_ = 0;
#define DEBUG_ASSERT(cond)
DART_FORCE_INLINE bool operator==(const Iterator &other) const
DART_FORCE_INLINE T & operator*() const
DART_FORCE_INLINE Iterator & operator++()
DART_FORCE_INLINE void Delete()
Iterator(PortSet< T > *ports, intptr_t index)
DART_FORCE_INLINE bool operator!=(const Iterator &other) const
DART_FORCE_INLINE T & operator->() const
void Insert(const T &entry)
static constexpr Dart_Port kDeletedPort
Iterator TryLookup(Dart_Port port)
DART_FORCE_INLINE Iterator begin()
DART_FORCE_INLINE Iterator end()
bool Contains(Dart_Port port)
static constexpr Dart_Port kFreePort
static constexpr bool IsPowerOfTwo(T x)
EMSCRIPTEN_KEEPALIVE void empty()
DEF_SWITCHES_START aot vmservice shared library Name of the *so containing AOT compiled Dart assets for launching the service isolate vm snapshot The VM snapshot data that will be memory mapped as read only SnapshotAssetPath must be present isolate snapshot The isolate snapshot data that will be memory mapped as read only SnapshotAssetPath must be present cache dir Path to the cache directory This is different from the persistent_cache_path in embedder which is used for Skia shader cache icu native lib Path to the library file that exports the ICU data vm service The hostname IP address on which the Dart VM Service should be served If not defaults to or::depending on whether ipv6 is specified vm service port